| commit | 246313bf2738732bc6512edf9dca27a3db0b30ab | [log] [tgz] |
|---|---|---|
| author | Emmmer <yjhdandan@163.com> | Mon Aug 01 18:02:06 2022 +0800 |
| committer | Copybara-Service <copybara-worker@google.com> | Mon Aug 01 21:01:52 2022 -0700 |
| tree | f429f9079cfb5ba54bd67e76be2a36bccee9b886 | |
| parent | e1b38797a8e8d272f7fffb17d1cb0a8731501eee [diff] |
[LLDB][RISCV] Add riscv register enums According to [RISC-V ISA Spec](https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf) and [riscv-v-spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model) Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D130899 GitOrigin-RevId: 768e59d959c7e23e98cda1b08c5b6b68dbc1d2a7