diff --git a/include/__libunwind_config.h b/include/__libunwind_config.h
index 34ac6f7..a50ba05 100644
--- a/include/__libunwind_config.h
+++ b/include/__libunwind_config.h
@@ -131,12 +131,19 @@
   #define _LIBUNWIND_CONTEXT_SIZE 16
   #define _LIBUNWIND_CURSOR_SIZE 23
 # elif defined(__riscv)
-#  if __riscv_xlen == 64
-#    define _LIBUNWIND_TARGET_RISCV 1
-#    define _LIBUNWIND_CONTEXT_SIZE 64
-#    define _LIBUNWIND_CURSOR_SIZE 76
+#  define _LIBUNWIND_TARGET_RISCV 1
+#  if defined(__riscv_flen)
+#   define RISCV_FLEN __riscv_flen
 #  else
-#    error "Unsupported RISC-V ABI"
+#   define RISCV_FLEN 0
+#  endif
+#  define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64)
+#  if __riscv_xlen == 32
+#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7)
+#  elif __riscv_xlen == 64
+#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12)
+#  else
+#   error "Unsupported RISC-V ABI"
 #  endif
 # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
 # elif defined(__ve__)
diff --git a/src/Registers.hpp b/src/Registers.hpp
index de8e067..1d23f97 100644
--- a/src/Registers.hpp
+++ b/src/Registers.hpp
@@ -3728,19 +3728,42 @@
 
 
 #if defined(_LIBUNWIND_TARGET_RISCV)
-/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
+/// Registers_riscv holds the register state of a thread in a RISC-V
 /// process.
+
+# if __riscv_xlen == 32
+typedef uint32_t reg_t;
+# elif __riscv_xlen == 64
+typedef uint64_t reg_t;
+# else
+#  error "Unsupported __riscv_xlen"
+# endif
+
+# if defined(__riscv_flen)
+#  if __riscv_flen == 64
+typedef double fp_t;
+#  elif __riscv_flen == 32
+typedef float fp_t;
+#  else
+#   error "Unsupported __riscv_flen"
+#  endif
+# else
+// This is just for supressing undeclared error of fp_t.
+typedef double fp_t;
+# endif
+
+/// Registers_riscv holds the register state of a thread.
 class _LIBUNWIND_HIDDEN Registers_riscv {
 public:
   Registers_riscv();
   Registers_riscv(const void *registers);
 
   bool        validRegister(int num) const;
-  uint64_t    getRegister(int num) const;
-  void        setRegister(int num, uint64_t value);
+  reg_t       getRegister(int num) const;
+  void        setRegister(int num, reg_t value);
   bool        validFloatRegister(int num) const;
-  double      getFloatRegister(int num) const;
-  void        setFloatRegister(int num, double value);
+  fp_t        getFloatRegister(int num) const;
+  void        setFloatRegister(int num, fp_t value);
   bool        validVectorRegister(int num) const;
   v128        getVectorRegister(int num) const;
   void        setVectorRegister(int num, v128 value);
@@ -3749,31 +3772,45 @@
   static int  lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV; }
   static int  getArch() { return REGISTERS_RISCV; }
 
-  uint64_t  getSP() const         { return _registers[2]; }
-  void      setSP(uint64_t value) { _registers[2] = value; }
-  uint64_t  getIP() const         { return _registers[0]; }
-  void      setIP(uint64_t value) { _registers[0] = value; }
+  reg_t       getSP() const { return _registers[2]; }
+  void        setSP(reg_t value) { _registers[2] = value; }
+  reg_t       getIP() const { return _registers[0]; }
+  void        setIP(reg_t value) { _registers[0] = value; }
 
 private:
   // _registers[0] holds the pc
-  uint64_t _registers[32];
-  double   _floats[32];
+  reg_t _registers[32];
+# if defined(__riscv_flen)
+  fp_t _floats[32];
+# endif
 };
 
 inline Registers_riscv::Registers_riscv(const void *registers) {
   static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit),
                 "riscv registers do not fit into unw_context_t");
   memcpy(&_registers, registers, sizeof(_registers));
+# if __riscv_xlen == 32
+  static_assert(sizeof(_registers) == 0x80,
+                "expected float registers to be at offset 128");
+# elif __riscv_xlen == 64
   static_assert(sizeof(_registers) == 0x100,
                 "expected float registers to be at offset 256");
+# else
+# error "Unexpected float registers."
+# endif
+
+# if defined(__riscv_flen)
   memcpy(_floats,
          static_cast<const uint8_t *>(registers) + sizeof(_registers),
          sizeof(_floats));
+# endif
 }
 
 inline Registers_riscv::Registers_riscv() {
   memset(&_registers, 0, sizeof(_registers));
+# if defined(__riscv_flen)
   memset(&_floats, 0, sizeof(_floats));
+# endif
 }
 
 inline bool Registers_riscv::validRegister(int regNum) const {
@@ -3788,7 +3825,7 @@
   return true;
 }
 
-inline uint64_t Registers_riscv::getRegister(int regNum) const {
+inline reg_t Registers_riscv::getRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return _registers[0];
   if (regNum == UNW_REG_SP)
@@ -3800,7 +3837,7 @@
   _LIBUNWIND_ABORT("unsupported riscv register");
 }
 
-inline void Registers_riscv::setRegister(int regNum, uint64_t value) {
+inline void Registers_riscv::setRegister(int regNum, reg_t value) {
   if (regNum == UNW_REG_IP)
     _registers[0] = value;
   else if (regNum == UNW_REG_SP)
@@ -3954,32 +3991,37 @@
 }
 
 inline bool Registers_riscv::validFloatRegister(int regNum) const {
+# if defined(__riscv_flen)
   if (regNum < UNW_RISCV_F0)
     return false;
   if (regNum > UNW_RISCV_F31)
     return false;
   return true;
+# else
+  (void)regNum;
+  return false;
+# endif
 }
 
-inline double Registers_riscv::getFloatRegister(int regNum) const {
-#if defined(__riscv_flen) && __riscv_flen == 64
+inline fp_t Registers_riscv::getFloatRegister(int regNum) const {
+# if defined(__riscv_flen)
   assert(validFloatRegister(regNum));
   return _floats[regNum - UNW_RISCV_F0];
-#else
+# else
   (void)regNum;
   _LIBUNWIND_ABORT("libunwind not built with float support");
-#endif
+# endif
 }
 
-inline void Registers_riscv::setFloatRegister(int regNum, double value) {
-#if defined(__riscv_flen) && __riscv_flen == 64
+inline void Registers_riscv::setFloatRegister(int regNum, fp_t value) {
+# if defined(__riscv_flen)
   assert(validFloatRegister(regNum));
   _floats[regNum - UNW_RISCV_F0] = value;
-#else
+# else
   (void)regNum;
   (void)value;
   _LIBUNWIND_ABORT("libunwind not built with float support");
-#endif
+# endif
 }
 
 inline bool Registers_riscv::validVectorRegister(int) const {
diff --git a/src/UnwindRegistersRestore.S b/src/UnwindRegistersRestore.S
index 289afe9..6d12d93 100644
--- a/src/UnwindRegistersRestore.S
+++ b/src/UnwindRegistersRestore.S
@@ -1072,7 +1072,7 @@
   jmp %o7
    nop
 
-#elif defined(__riscv) && __riscv_xlen == 64
+#elif defined(__riscv)
 
 //
 // void libunwind::Registers_riscv::jumpto()
@@ -1082,74 +1082,74 @@
 //
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
-#if defined(__riscv_flen) && __riscv_flen == 64
-  fld    f0, (8 * 32 + 8 * 0)(a0)
-  fld    f1, (8 * 32 + 8 * 1)(a0)
-  fld    f2, (8 * 32 + 8 * 2)(a0)
-  fld    f3, (8 * 32 + 8 * 3)(a0)
-  fld    f4, (8 * 32 + 8 * 4)(a0)
-  fld    f5, (8 * 32 + 8 * 5)(a0)
-  fld    f6, (8 * 32 + 8 * 6)(a0)
-  fld    f7, (8 * 32 + 8 * 7)(a0)
-  fld    f8, (8 * 32 + 8 * 8)(a0)
-  fld    f9, (8 * 32 + 8 * 9)(a0)
-  fld    f10, (8 * 32 + 8 * 10)(a0)
-  fld    f11, (8 * 32 + 8 * 11)(a0)
-  fld    f12, (8 * 32 + 8 * 12)(a0)
-  fld    f13, (8 * 32 + 8 * 13)(a0)
-  fld    f14, (8 * 32 + 8 * 14)(a0)
-  fld    f15, (8 * 32 + 8 * 15)(a0)
-  fld    f16, (8 * 32 + 8 * 16)(a0)
-  fld    f17, (8 * 32 + 8 * 17)(a0)
-  fld    f18, (8 * 32 + 8 * 18)(a0)
-  fld    f19, (8 * 32 + 8 * 19)(a0)
-  fld    f20, (8 * 32 + 8 * 20)(a0)
-  fld    f21, (8 * 32 + 8 * 21)(a0)
-  fld    f22, (8 * 32 + 8 * 22)(a0)
-  fld    f23, (8 * 32 + 8 * 23)(a0)
-  fld    f24, (8 * 32 + 8 * 24)(a0)
-  fld    f25, (8 * 32 + 8 * 25)(a0)
-  fld    f26, (8 * 32 + 8 * 26)(a0)
-  fld    f27, (8 * 32 + 8 * 27)(a0)
-  fld    f28, (8 * 32 + 8 * 28)(a0)
-  fld    f29, (8 * 32 + 8 * 29)(a0)
-  fld    f30, (8 * 32 + 8 * 30)(a0)
-  fld    f31, (8 * 32 + 8 * 31)(a0)
-#endif
+# if defined(__riscv_flen)
+  FLOAD    f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0)
+  FLOAD    f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0)
+  FLOAD    f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0)
+  FLOAD    f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0)
+  FLOAD    f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0)
+  FLOAD    f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0)
+  FLOAD    f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0)
+  FLOAD    f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0)
+  FLOAD    f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0)
+  FLOAD    f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0)
+  FLOAD    f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0)
+  FLOAD    f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0)
+  FLOAD    f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0)
+  FLOAD    f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0)
+  FLOAD    f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0)
+  FLOAD    f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0)
+  FLOAD    f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0)
+  FLOAD    f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0)
+  FLOAD    f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0)
+  FLOAD    f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0)
+  FLOAD    f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0)
+  FLOAD    f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0)
+  FLOAD    f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0)
+  FLOAD    f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0)
+  FLOAD    f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0)
+  FLOAD    f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0)
+  FLOAD    f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0)
+  FLOAD    f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0)
+  FLOAD    f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0)
+  FLOAD    f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0)
+  FLOAD    f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0)
+  FLOAD    f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0)
+# endif
 
   // x0 is zero
-  ld    x1, (8 * 0)(a0) // restore pc into ra
-  ld    x2, (8 * 2)(a0)
-  ld    x3, (8 * 3)(a0)
-  ld    x4, (8 * 4)(a0)
-  ld    x5, (8 * 5)(a0)
-  ld    x6, (8 * 6)(a0)
-  ld    x7, (8 * 7)(a0)
-  ld    x8, (8 * 8)(a0)
-  ld    x9, (8 * 9)(a0)
+  ILOAD    x1, (RISCV_ISIZE * 0)(a0) // restore pc into ra
+  ILOAD    x2, (RISCV_ISIZE * 2)(a0)
+  ILOAD    x3, (RISCV_ISIZE * 3)(a0)
+  ILOAD    x4, (RISCV_ISIZE * 4)(a0)
+  ILOAD    x5, (RISCV_ISIZE * 5)(a0)
+  ILOAD    x6, (RISCV_ISIZE * 6)(a0)
+  ILOAD    x7, (RISCV_ISIZE * 7)(a0)
+  ILOAD    x8, (RISCV_ISIZE * 8)(a0)
+  ILOAD    x9, (RISCV_ISIZE * 9)(a0)
   // skip a0 for now
-  ld    x11, (8 * 11)(a0)
-  ld    x12, (8 * 12)(a0)
-  ld    x13, (8 * 13)(a0)
-  ld    x14, (8 * 14)(a0)
-  ld    x15, (8 * 15)(a0)
-  ld    x16, (8 * 16)(a0)
-  ld    x17, (8 * 17)(a0)
-  ld    x18, (8 * 18)(a0)
-  ld    x19, (8 * 19)(a0)
-  ld    x20, (8 * 20)(a0)
-  ld    x21, (8 * 21)(a0)
-  ld    x22, (8 * 22)(a0)
-  ld    x23, (8 * 23)(a0)
-  ld    x24, (8 * 24)(a0)
-  ld    x25, (8 * 25)(a0)
-  ld    x26, (8 * 26)(a0)
-  ld    x27, (8 * 27)(a0)
-  ld    x28, (8 * 28)(a0)
-  ld    x29, (8 * 29)(a0)
-  ld    x30, (8 * 30)(a0)
-  ld    x31, (8 * 31)(a0)
-  ld    x10, (8 * 10)(a0)   // restore a0
+  ILOAD    x11, (RISCV_ISIZE * 11)(a0)
+  ILOAD    x12, (RISCV_ISIZE * 12)(a0)
+  ILOAD    x13, (RISCV_ISIZE * 13)(a0)
+  ILOAD    x14, (RISCV_ISIZE * 14)(a0)
+  ILOAD    x15, (RISCV_ISIZE * 15)(a0)
+  ILOAD    x16, (RISCV_ISIZE * 16)(a0)
+  ILOAD    x17, (RISCV_ISIZE * 17)(a0)
+  ILOAD    x18, (RISCV_ISIZE * 18)(a0)
+  ILOAD    x19, (RISCV_ISIZE * 19)(a0)
+  ILOAD    x20, (RISCV_ISIZE * 20)(a0)
+  ILOAD    x21, (RISCV_ISIZE * 21)(a0)
+  ILOAD    x22, (RISCV_ISIZE * 22)(a0)
+  ILOAD    x23, (RISCV_ISIZE * 23)(a0)
+  ILOAD    x24, (RISCV_ISIZE * 24)(a0)
+  ILOAD    x25, (RISCV_ISIZE * 25)(a0)
+  ILOAD    x26, (RISCV_ISIZE * 26)(a0)
+  ILOAD    x27, (RISCV_ISIZE * 27)(a0)
+  ILOAD    x28, (RISCV_ISIZE * 28)(a0)
+  ILOAD    x29, (RISCV_ISIZE * 29)(a0)
+  ILOAD    x30, (RISCV_ISIZE * 30)(a0)
+  ILOAD    x31, (RISCV_ISIZE * 31)(a0)
+  ILOAD    x10, (RISCV_ISIZE * 10)(a0)   // restore a0
 
   ret                       // jump to ra
 
diff --git a/src/UnwindRegistersSave.S b/src/UnwindRegistersSave.S
index 94fc836..ef39ac1 100644
--- a/src/UnwindRegistersSave.S
+++ b/src/UnwindRegistersSave.S
@@ -1026,7 +1026,7 @@
   jmp %o7
    clr %o0                   // return UNW_ESUCCESS
 
-#elif defined(__riscv) && __riscv_xlen == 64
+#elif defined(__riscv)
 
 #
 # extern int __unw_getcontext(unw_context_t* thread_state)
@@ -1035,73 +1035,73 @@
 #  thread_state pointer is in a0
 #
 DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
-  sd    x1, (8 * 0)(a0) // store ra as pc
-  sd    x1, (8 * 1)(a0)
-  sd    x2, (8 * 2)(a0)
-  sd    x3, (8 * 3)(a0)
-  sd    x4, (8 * 4)(a0)
-  sd    x5, (8 * 5)(a0)
-  sd    x6, (8 * 6)(a0)
-  sd    x7, (8 * 7)(a0)
-  sd    x8, (8 * 8)(a0)
-  sd    x9, (8 * 9)(a0)
-  sd    x10, (8 * 10)(a0)
-  sd    x11, (8 * 11)(a0)
-  sd    x12, (8 * 12)(a0)
-  sd    x13, (8 * 13)(a0)
-  sd    x14, (8 * 14)(a0)
-  sd    x15, (8 * 15)(a0)
-  sd    x16, (8 * 16)(a0)
-  sd    x17, (8 * 17)(a0)
-  sd    x18, (8 * 18)(a0)
-  sd    x19, (8 * 19)(a0)
-  sd    x20, (8 * 20)(a0)
-  sd    x21, (8 * 21)(a0)
-  sd    x22, (8 * 22)(a0)
-  sd    x23, (8 * 23)(a0)
-  sd    x24, (8 * 24)(a0)
-  sd    x25, (8 * 25)(a0)
-  sd    x26, (8 * 26)(a0)
-  sd    x27, (8 * 27)(a0)
-  sd    x28, (8 * 28)(a0)
-  sd    x29, (8 * 29)(a0)
-  sd    x30, (8 * 30)(a0)
-  sd    x31, (8 * 31)(a0)
+  ISTORE    x1, (RISCV_ISIZE * 0)(a0) // store ra as pc
+  ISTORE    x1, (RISCV_ISIZE * 1)(a0)
+  ISTORE    x2, (RISCV_ISIZE * 2)(a0)
+  ISTORE    x3, (RISCV_ISIZE * 3)(a0)
+  ISTORE    x4, (RISCV_ISIZE * 4)(a0)
+  ISTORE    x5, (RISCV_ISIZE * 5)(a0)
+  ISTORE    x6, (RISCV_ISIZE * 6)(a0)
+  ISTORE    x7, (RISCV_ISIZE * 7)(a0)
+  ISTORE    x8, (RISCV_ISIZE * 8)(a0)
+  ISTORE    x9, (RISCV_ISIZE * 9)(a0)
+  ISTORE    x10, (RISCV_ISIZE * 10)(a0)
+  ISTORE    x11, (RISCV_ISIZE * 11)(a0)
+  ISTORE    x12, (RISCV_ISIZE * 12)(a0)
+  ISTORE    x13, (RISCV_ISIZE * 13)(a0)
+  ISTORE    x14, (RISCV_ISIZE * 14)(a0)
+  ISTORE    x15, (RISCV_ISIZE * 15)(a0)
+  ISTORE    x16, (RISCV_ISIZE * 16)(a0)
+  ISTORE    x17, (RISCV_ISIZE * 17)(a0)
+  ISTORE    x18, (RISCV_ISIZE * 18)(a0)
+  ISTORE    x19, (RISCV_ISIZE * 19)(a0)
+  ISTORE    x20, (RISCV_ISIZE * 20)(a0)
+  ISTORE    x21, (RISCV_ISIZE * 21)(a0)
+  ISTORE    x22, (RISCV_ISIZE * 22)(a0)
+  ISTORE    x23, (RISCV_ISIZE * 23)(a0)
+  ISTORE    x24, (RISCV_ISIZE * 24)(a0)
+  ISTORE    x25, (RISCV_ISIZE * 25)(a0)
+  ISTORE    x26, (RISCV_ISIZE * 26)(a0)
+  ISTORE    x27, (RISCV_ISIZE * 27)(a0)
+  ISTORE    x28, (RISCV_ISIZE * 28)(a0)
+  ISTORE    x29, (RISCV_ISIZE * 29)(a0)
+  ISTORE    x30, (RISCV_ISIZE * 30)(a0)
+  ISTORE    x31, (RISCV_ISIZE * 31)(a0)
 
-#if defined(__riscv_flen) && __riscv_flen == 64
-  fsd    f0, (8 * 32 + 8 * 0)(a0)
-  fsd    f1, (8 * 32 + 8 * 1)(a0)
-  fsd    f2, (8 * 32 + 8 * 2)(a0)
-  fsd    f3, (8 * 32 + 8 * 3)(a0)
-  fsd    f4, (8 * 32 + 8 * 4)(a0)
-  fsd    f5, (8 * 32 + 8 * 5)(a0)
-  fsd    f6, (8 * 32 + 8 * 6)(a0)
-  fsd    f7, (8 * 32 + 8 * 7)(a0)
-  fsd    f8, (8 * 32 + 8 * 8)(a0)
-  fsd    f9, (8 * 32 + 8 * 9)(a0)
-  fsd    f10, (8 * 32 + 8 * 10)(a0)
-  fsd    f11, (8 * 32 + 8 * 11)(a0)
-  fsd    f12, (8 * 32 + 8 * 12)(a0)
-  fsd    f13, (8 * 32 + 8 * 13)(a0)
-  fsd    f14, (8 * 32 + 8 * 14)(a0)
-  fsd    f15, (8 * 32 + 8 * 15)(a0)
-  fsd    f16, (8 * 32 + 8 * 16)(a0)
-  fsd    f17, (8 * 32 + 8 * 17)(a0)
-  fsd    f18, (8 * 32 + 8 * 18)(a0)
-  fsd    f19, (8 * 32 + 8 * 19)(a0)
-  fsd    f20, (8 * 32 + 8 * 20)(a0)
-  fsd    f21, (8 * 32 + 8 * 21)(a0)
-  fsd    f22, (8 * 32 + 8 * 22)(a0)
-  fsd    f23, (8 * 32 + 8 * 23)(a0)
-  fsd    f24, (8 * 32 + 8 * 24)(a0)
-  fsd    f25, (8 * 32 + 8 * 25)(a0)
-  fsd    f26, (8 * 32 + 8 * 26)(a0)
-  fsd    f27, (8 * 32 + 8 * 27)(a0)
-  fsd    f28, (8 * 32 + 8 * 28)(a0)
-  fsd    f29, (8 * 32 + 8 * 29)(a0)
-  fsd    f30, (8 * 32 + 8 * 30)(a0)
-  fsd    f31, (8 * 32 + 8 * 31)(a0)
-#endif
+# if defined(__riscv_flen)
+  FSTORE    f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0)
+  FSTORE    f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0)
+  FSTORE    f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0)
+  FSTORE    f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0)
+  FSTORE    f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0)
+  FSTORE    f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0)
+  FSTORE    f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0)
+  FSTORE    f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0)
+  FSTORE    f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0)
+  FSTORE    f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0)
+  FSTORE    f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0)
+  FSTORE    f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0)
+  FSTORE    f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0)
+  FSTORE    f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0)
+  FSTORE    f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0)
+  FSTORE    f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0)
+  FSTORE    f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0)
+  FSTORE    f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0)
+  FSTORE    f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0)
+  FSTORE    f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0)
+  FSTORE    f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0)
+  FSTORE    f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0)
+  FSTORE    f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0)
+  FSTORE    f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0)
+  FSTORE    f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0)
+  FSTORE    f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0)
+  FSTORE    f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0)
+  FSTORE    f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0)
+  FSTORE    f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0)
+  FSTORE    f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0)
+  FSTORE    f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0)
+  FSTORE    f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0)
+# endif
 
   li     a0, 0  // return UNW_ESUCCESS
   ret           // jump to ra
diff --git a/src/assembly.h b/src/assembly.h
index dcd3819..f5ca35c 100644
--- a/src/assembly.h
+++ b/src/assembly.h
@@ -27,6 +27,35 @@
 #define PPC64_OFFS_V      824
 #elif defined(__APPLE__) && defined(__aarch64__)
 #define SEPARATOR %%
+#elif defined(__riscv)
+# define RISCV_ISIZE (__riscv_xlen / 8)
+# define RISCV_FOFFSET (RISCV_ISIZE * 32)
+# if defined(__riscv_flen)
+#  define RISCV_FSIZE (__riscv_flen / 8)
+# endif
+
+# if __riscv_xlen == 64
+#  define ILOAD ld
+#  define ISTORE sd
+# elif __riscv_xlen == 32
+#  define ILOAD lw
+#  define ISTORE sw
+# else
+#  error "Unsupported __riscv_xlen"
+# endif
+
+# if defined(__riscv_flen)
+#  if __riscv_flen == 64
+#   define FLOAD fld
+#   define FSTORE fsd
+#  elif __riscv_flen == 32
+#   define FLOAD flw
+#   define FSTORE fsw
+#  else
+#   error "Unsupported __riscv_flen"
+#  endif
+# endif
+# define SEPARATOR ;
 #else
 #define SEPARATOR ;
 #endif
diff --git a/src/libunwind.cpp b/src/libunwind.cpp
index c21461b..eb2623e 100644
--- a/src/libunwind.cpp
+++ b/src/libunwind.cpp
@@ -60,7 +60,7 @@
 # warning The MIPS architecture is not supported with this ABI and environment!
 #elif defined(__sparc__)
 # define REGISTER_KIND Registers_sparc
-#elif defined(__riscv) && __riscv_xlen == 64
+#elif defined(__riscv)
 # define REGISTER_KIND Registers_riscv
 #elif defined(__ve__)
 # define REGISTER_KIND Registers_ve