diff --git a/src/Registers.hpp b/src/Registers.hpp
index 4d963b4..e0cb84f 100644
--- a/src/Registers.hpp
+++ b/src/Registers.hpp
@@ -1514,12 +1514,12 @@
 }
 
 inline bool Registers_ppc64::validVectorRegister(int regNum) const {
-#ifdef PPC64_HAS_VMX
+#if defined(__VSX__)
   if (regNum >= UNW_PPC64_VS0 && regNum <= UNW_PPC64_VS31)
     return true;
   if (regNum >= UNW_PPC64_VS32 && regNum <= UNW_PPC64_VS63)
     return true;
-#else
+#elif defined(__ALTIVEC__)
   if (regNum >= UNW_PPC64_V0 && regNum <= UNW_PPC64_V31)
     return true;
 #endif
diff --git a/src/UnwindRegistersRestore.S b/src/UnwindRegistersRestore.S
index d817e6d..289afe9 100644
--- a/src/UnwindRegistersRestore.S
+++ b/src/UnwindRegistersRestore.S
@@ -170,7 +170,7 @@
   PPC64_LR(30)
   PPC64_LR(31)
 
-#ifdef PPC64_HAS_VMX
+#if defined(__VSX__)
 
   // restore VS registers
   // (note that this also restores floating point registers and V registers,
@@ -312,6 +312,7 @@
   PPC64_LF(30)
   PPC64_LF(31)
 
+#if defined(__ALTIVEC__)
   // restore vector registers if any are in use
   ld    %r5, PPC64_OFFS_VRSAVE(%r3)   // test VRsave
   cmpwi %r5, 0
@@ -373,6 +374,7 @@
   PPC64_CLV_UNALIGNEDh(31)
 
 #endif
+#endif
 
 Lnovec:
   ld    %r0, PPC64_OFFS_CR(%r3)
@@ -431,6 +433,7 @@
   lwz     %r30,128(%r3)
   lwz     %r31,132(%r3)
 
+#ifndef __NO_FPRS__
   // restore float registers
   lfd     %f0, 160(%r3)
   lfd     %f1, 168(%r3)
@@ -464,7 +467,9 @@
   lfd     %f29,392(%r3)
   lfd     %f30,400(%r3)
   lfd     %f31,408(%r3)
+#endif
 
+#if defined(__ALTIVEC__)
   // restore vector registers if any are in use
   lwz     %r5, 156(%r3)       // test VRsave
   cmpwi   %r5, 0
@@ -537,6 +542,7 @@
   LOAD_VECTOR_UNALIGNEDh(29)
   LOAD_VECTOR_UNALIGNEDh(30)
   LOAD_VECTOR_UNALIGNEDh(31)
+#endif
 
 Lnovec:
   lwz     %r0, 136(%r3)   // __cr
diff --git a/src/UnwindRegistersSave.S b/src/UnwindRegistersSave.S
index 51bb9b0..94fc836 100644
--- a/src/UnwindRegistersSave.S
+++ b/src/UnwindRegistersSave.S
@@ -384,7 +384,7 @@
   mfvrsave    %r0
   std   %r0,  PPC64_OFFS_VRSAVE(%r3)
 
-#ifdef PPC64_HAS_VMX
+#if defined(__VSX__)
   // save VS registers
   // (note that this also saves floating point registers and V registers,
   // because part of VS is mapped to these registers)
@@ -501,6 +501,7 @@
   PPC64_STF(30)
   PPC64_STF(31)
 
+#if defined(__ALTIVEC__)
   // save vector registers
 
   // Use 16-bytes below the stack pointer as an
@@ -549,6 +550,7 @@
   PPC64_STV_UNALIGNED(31)
 
 #endif
+#endif
 
   li    %r3,  0   // return UNW_ESUCCESS
   blr
@@ -608,6 +610,7 @@
   mfctr   %r0
   stw     %r0, 148(%r3)
 
+#if !defined(__NO_FPRS__)
   // save float registers
   stfd    %f0, 160(%r3)
   stfd    %f1, 168(%r3)
@@ -641,8 +644,9 @@
   stfd    %f29,392(%r3)
   stfd    %f30,400(%r3)
   stfd    %f31,408(%r3)
+#endif
 
-
+#if defined(__ALTIVEC__)
   // save vector registers
 
   subi    %r4, %r1, 16
@@ -692,6 +696,7 @@
   SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0)
   SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0)
   SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0)
+#endif
 
   li      %r3, 0  // return UNW_ESUCCESS
   blr
diff --git a/src/assembly.h b/src/assembly.h
index 3b1e6e6..f2f7c84 100644
--- a/src/assembly.h
+++ b/src/assembly.h
@@ -25,9 +25,6 @@
 #define PPC64_OFFS_VRSAVE 304
 #define PPC64_OFFS_FP     312
 #define PPC64_OFFS_V      824
-#ifdef _ARCH_PWR8
-#define PPC64_HAS_VMX
-#endif
 #elif defined(__APPLE__) && defined(__aarch64__)
 #define SEPARATOR %%
 #else
diff --git a/src/config.h b/src/config.h
index e20d51a..9efed05 100644
--- a/src/config.h
+++ b/src/config.h
@@ -116,10 +116,6 @@
 #endif
 #endif
 
-#if defined(__powerpc64__) && defined(_ARCH_PWR8)
-#define PPC64_HAS_VMX
-#endif
-
 #ifndef _LIBUNWIND_REMEMBER_HEAP_ALLOC
 #if defined(_LIBUNWIND_REMEMBER_STACK_ALLOC) || defined(__APPLE__) ||          \
     defined(__linux__) || defined(__ANDROID__) || defined(__MINGW32__) ||      \