[libclc] Add optimized DPP scan functions for AMDGPU (#197543)

Summary:
This uses the update_dpp function to efficiently provide scans. DPP
allows for swizzling within a group of 16, so we do four of those,
followed by a permlane on GFX10, or a native DPP shift on GFX9.

 Right now these are not actually used because we do not compile for
 multiple targets yet, but I verified them by setting
 `CMAKE_CLC_FLAGS=mcpu=gfx1030` or similar. The intention is to have
 these waiting as a motivational implementation once we start doing
 variable builds.

 The output is optimal as far as I am aware. Here is the example for
 gfx1030 generation:

 ```asm
_Z28sub_group_scan_inclusive_addi: ; @_Z28sub_group_scan_inclusive_addi
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, s33
	s_mov_b32 s33, s32
	s_mov_b32 s33, s4
v_add_nc_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
bound_ctrl:1
v_add_nc_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
bound_ctrl:1
v_add_nc_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
bound_ctrl:1
v_add_nc_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
bound_ctrl:1
	v_permlanex16_b32 v1, v0, -1, -1
v_add_nc_u32_dpp v0, v1, v0 quad_perm:[0,1,2,3] row_mask:0xa
bank_mask:0xf
	s_setpc_b64 s[30:31]
 ```
GitOrigin-RevId: f230e44ab888a3688d99ac5f28a2e3edbf3aa596