| commit | 4bdc90fef80e81ee77584f678adca40a6d1cbb7d | [log] [tgz] |
|---|---|---|
| author | Cyrill Leutwiler <bigcyrill@hotmail.com> | Thu Apr 11 07:11:51 2024 +0200 |
| committer | Copybara-Service <copybara-worker@google.com> | Wed Apr 10 22:17:43 2024 -0700 |
| tree | 4661b018987be5689b8c1572ca6c9d96bace6fe3 | |
| parent | f26fdd8131cbbdaf7478ac2dfed2121193566d62 [diff] |
[RISCV] Support rv{32, 64}e in the compiler builtins (#88252)
Register spills (save/restore) in RISC-V embedded work differently
because there are less registers and different stack alignment.
[GCC equivalent
](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336)
Follow up from #76777.
---------
Signed-off-by: xermicus <cyrill@parity.io>
GitOrigin-RevId: bd32aaa8c9ec2094f605315b3989adc2a567ca98