8cca34ea0ab6f0366a5b90f1a77b565fe2a8f7bc - llvm-project/clang

commit	8cca34ea0ab6f0366a5b90f1a77b565fe2a8f7bc	[log] [tgz]
author	Zakk Chen <zakk.chen@sifive.com>	Mon Mar 29 07:37:29 2021 -0700
committer	Copybara-Service <copybara-worker@google.com>	Mon Apr 12 11:04:11 2021 -0700
tree	2b58d2283a1e67cd6787626e175fcacf33ce6a81
parent	5f9054a99e72ad305726ef02b0d7fa44d6399f3d [diff]

[RISCV][Clang] Add some RVV Integer intrinsic functions.

1. Rename RVVBinBuiltin to RVVOutputOp1Builtin because it is not related
to the number of operand.
2. Add RVV Integer instuctions which use RVVOutputOp1Builtin.

Reviewed By: craig.topper

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99524

GitOrigin-RevId: 66c05609e0d5b758295b3c20d3dde4f3c3cda673

include/clang/Basic/riscv_vector.td[diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vand.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vdiv.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vmacc.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vmadd.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vmax.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vmin.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vmul.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vor.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vrem.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vrsub.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vsll.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vsra.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vsrl.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vsub.c[Added - diff]
test/CodeGen/RISCV/rvv-intrinsics/vxor.c[Added - diff]

35 files changed

tree: 2b58d2283a1e67cd6787626e175fcacf33ce6a81