tree 796e6087032ab8480c9d32c5881f02615e927edc
parent 14f1023d2a58aa403e2e85b89d2ac0d1847e0fb6
author Frank Derry Wanye <wanyef@mail.gvsu.edu> 1604329898 -0500
committer Copybara-Service <copybara-worker@google.com> 1604341195 -0800

Add a new altera kernel name restriction check to clang-tidy.

The altera kernel name restriction check finds kernel files and include
directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl".
Such kernel file names cause the Altera Offline Compiler to generate
intermediate design files that have the same names as certain internal
files, which leads to a compilation error.

As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA
SDK for OpenCL Pro Edition: Programming Guide."

GitOrigin-RevId: 43a38a65233039b5e71797a644d41a890f8d7f2b