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llvm/llvm-project/refs/heads/users/cdevadas/subreg-reload/llvm/test/CodeGen/AMDGPU/fabs.ll
  1. 9c78bc5 Revert "[LSV] Merge contiguous chains across scalar types" (#170381) by Drew Kersnar · 4 months ago
  2. fbdf8ab [LSV] Merge contiguous chains across scalar types (#154069) by Anshil Gandhi · 4 months ago
  3. e95f6fa RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621) by Matt Arsenault · 5 months ago
  4. 6548b63 Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)" by Shilei Tian · 1 year, 5 months ago
  5. ca33649 Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)" by Shilei Tian · 1 year, 5 months ago
  6. e215a1e [AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403) by Shilei Tian · 1 year, 5 months ago
  7. b1bcb7c Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851) by Matt Arsenault · 1 year, 9 months ago
  8. adaff46 Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851) by dyung · 1 year, 9 months ago
  9. 78bc1b6 AMDGPU: Move attributor into optimization pipeline (#83131) by Matt Arsenault · 1 year, 9 months ago
  10. e96e7f1 [AMDGPU] Auto-generated some lit test patterns (NFC). (#94310) by Christudasan Devadasan · 1 year, 10 months ago
  11. 177ff42 AMDGPU: Convert some fp op tests to opaque issues by Matt Arsenault · 3 years, 4 months ago
  12. 0dcfe7a [InstCombine] Tighten up known library function signature tests (PR #56463) by Martin Sebor · 3 years, 9 months ago
  13. 4c4db81 [AMDGPU] Extend SILoadStoreOptimizer to s_load instructions by Carl Ritson · 3 years, 8 months ago
  14. 3eb2281 [AMDGPU] Aggressively fold immediates in SIFoldOperands by Jay Foad · 3 years, 11 months ago
  15. f510045 [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. by Jay Foad · 4 years, 3 months ago
  16. da067ed [AMDGPU] Set most sched model resource's BufferSize to one by Austin Kerbow · 4 years, 5 months ago
  17. f4ace63 AMDGPU: Add target id and code object v4 support by Konstantin Zhuravlyov · 5 years ago
  18. 27df165 Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel." by Matt Arsenault · 6 years ago
  19. c3492a1 [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel. by Michael Liao · 6 years ago
  20. c4d256a [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.' by Alexander Timofeev · 6 years ago
  21. 37bd9bd [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd by Alexander Timofeev · 7 years ago
  22. ba447ba [AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence. by Alexander Timofeev · 7 years ago
  23. 3b93737 Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence." by Peter Collingbourne · 7 years ago
  24. dffedea [AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence. by Alexander Timofeev · 7 years ago
  25. b297379e [AMDGPU] Shrink scalar AND, OR, XOR instructions by Graham Sellers · 7 years ago
  26. 8c4a352 AMDGPU: Add pass to lower kernel arguments to loads by Matt Arsenault · 8 years ago
  27. 697300b AMDGPU: Use scalar operations for f16 fabs/fneg patterns by Matt Arsenault · 8 years ago
  28. e11d8ac AMDGPU: Implement hasBitPreservingFPLogic by Matt Arsenault · 8 years ago
  29. 56ea488 [AMDGPU] Allow SDWA in instructions with immediates and SGPRs by Stanislav Mekhanoshin · 9 years ago
  30. 3dbeefa AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel by Matt Arsenault · 9 years ago
  31. 7aad8fd Enable FeatureFlatForGlobal on Volcanic Islands by Matt Arsenault · 9 years ago
  32. bbb47da AMDGPU: Support commuting with immediate in src0 by Matt Arsenault · 10 years ago
  33. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 11 years ago[Renamed from llvm/test/CodeGen/R600/fabs.ll]
  34. fa6607d R600/SI: Enable a lot of existing tests for VI (squashed commits) by Marek Olsak · 11 years ago
  35. 49f8bfd R600/SI: Add a stub GCNTargetMachine by Tom Stellard · 11 years ago
  36. 326d6ec R600/SI: Change all instruction assembly names to lowercase. by Tom Stellard · 11 years ago
  37. 79243d9 R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table by Tom Stellard · 12 years ago
  38. fabf545 R600/SI: Move all fabs / fneg handling to patterns by Matt Arsenault · 12 years ago
  39. 06bd393 R600: Cleanup test by Matt Arsenault · 12 years ago
  40. b4a313a R600/SI: Do abs/neg folding with ComplexPatterns by Tom Stellard · 12 years ago
  41. 29c0c21 R600/SI: Fold fabs/fneg into src input modifier by Vincent Lejeune · 12 years ago
  42. 624b02a R600/SI: Fix fneg for 0.0 by Michel Danzer · 12 years ago
  43. 175e7a8 R600: Expand vector FABS by Tom Stellard · 12 years ago
  44. 72b31ee R600/SI: Change formatting of printed registers. by Matt Arsenault · 12 years ago
  45. 70f13db R600/SI: Use -verify-machineinstrs for most tests by Tom Stellard · 12 years ago
  46. c54731a DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free by Tom Stellard · 13 years ago
  47. 4b5b849 R600: Schedule copy from phys register at beginning of block by Vincent Lejeune · 13 years ago
  48. f83df1f R600: use capital letter for PV channel by Vincent Lejeune · 13 years ago
  49. 3d5118c R600: Use bottom up scheduling algorithm by Vincent Lejeune · 13 years ago
  50. f97af79 R600: Prettier asmPrint of Alu by Vincent Lejeune · 13 years ago
  51. 75aadc2 Add R600 backend by Tom Stellard · 13 years ago