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llvm / llvm-project / cbd445e4a331114752093746e9d596dafb8580b8 / llvm / test / CodeGen / RISCV / rvv / vfncvt-f-x-rv32.ll
  1. 0a9b829 [RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype. by Hsiangkai Wang · 4 years ago
  2. facff46 [RISCV] Reorder the vector register allocation order. by Hsiangkai Wang · 3 years, 9 months ago
  3. 7d39a8a [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics. by Hsiangkai Wang · 3 years, 10 months ago
  4. 242ddd5 [RISCV][NFC] Add a single space after comma for VType by Jim Lin · 4 years ago
  5. fdf10e6 [RISCV] Use X0 as destination of inserted vsetvli when possible. by Craig Topper · 4 years, 1 month ago
  6. d63d662 [RISCV] Remove --riscv-no-aliases from RVV tests by Jessica Clarke · 4 years, 1 month ago
  7. 5a9a8c7c [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC by Craig Topper · 4 years, 3 months ago
  8. 6e36046 [RISCV] Use v8-v23 as argument registers to conform to the proposal. by Hsiangkai Wang · 4 years, 5 months ago
  9. 2aed9bc [RISCV] Define vector narrowing type-convert intrinsic. by Monk Chiang · 4 years, 6 months ago