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llvm / llvm-project / refs/heads/users/optimisan/amdgpu-support-regalloc-options / . / llvm / lib / Target / RISCV
tree: 9a5b27f891225838da6fa9b6a5bbb3d361c84559 [path history] [tgz]
  1. AsmParser/
  2. Disassembler/
  3. GISel/
  4. MCA/
  5. MCTargetDesc/
  6. TargetInfo/
  7. CMakeLists.txt
  8. RISCV.h
  9. RISCV.td
  10. RISCVAsmPrinter.cpp
  11. RISCVCallingConv.cpp
  12. RISCVCallingConv.h
  13. RISCVCallingConv.td
  14. RISCVCodeGenPrepare.cpp
  15. RISCVCombine.td
  16. RISCVConstantPoolValue.cpp
  17. RISCVConstantPoolValue.h
  18. RISCVDeadRegisterDefinitions.cpp
  19. RISCVExpandAtomicPseudoInsts.cpp
  20. RISCVExpandPseudoInsts.cpp
  21. RISCVFeatures.td
  22. RISCVFoldMemOffset.cpp
  23. RISCVFrameLowering.cpp
  24. RISCVFrameLowering.h
  25. RISCVGatherScatterLowering.cpp
  26. RISCVGISel.td
  27. RISCVIndirectBranchTracking.cpp
  28. RISCVInsertReadWriteCSR.cpp
  29. RISCVInsertVSETVLI.cpp
  30. RISCVInsertWriteVXRM.cpp
  31. RISCVInstrFormats.td
  32. RISCVInstrFormatsC.td
  33. RISCVInstrFormatsV.td
  34. RISCVInstrGISel.td
  35. RISCVInstrInfo.cpp
  36. RISCVInstrInfo.h
  37. RISCVInstrInfo.td
  38. RISCVInstrInfoA.td
  39. RISCVInstrInfoC.td
  40. RISCVInstrInfoD.td
  41. RISCVInstrInfoF.td
  42. RISCVInstrInfoM.td
  43. RISCVInstrInfoSFB.td
  44. RISCVInstrInfoV.td
  45. RISCVInstrInfoVPseudos.td
  46. RISCVInstrInfoVSDPatterns.td
  47. RISCVInstrInfoVVLPatterns.td
  48. RISCVInstrInfoXCV.td
  49. RISCVInstrInfoXMips.td
  50. RISCVInstrInfoXqccmp.td
  51. RISCVInstrInfoXqci.td
  52. RISCVInstrInfoXRivos.td
  53. RISCVInstrInfoXSf.td
  54. RISCVInstrInfoXTHead.td
  55. RISCVInstrInfoXVentana.td
  56. RISCVInstrInfoXwch.td
  57. RISCVInstrInfoZa.td
  58. RISCVInstrInfoZalasr.td
  59. RISCVInstrInfoZb.td
  60. RISCVInstrInfoZc.td
  61. RISCVInstrInfoZcmop.td
  62. RISCVInstrInfoZfa.td
  63. RISCVInstrInfoZfbfmin.td
  64. RISCVInstrInfoZfh.td
  65. RISCVInstrInfoZicbo.td
  66. RISCVInstrInfoZicfiss.td
  67. RISCVInstrInfoZicond.td
  68. RISCVInstrInfoZimop.td
  69. RISCVInstrInfoZk.td
  70. RISCVInstrInfoZvfbf.td
  71. RISCVInstrInfoZvk.td
  72. RISCVISelDAGToDAG.cpp
  73. RISCVISelDAGToDAG.h
  74. RISCVISelLowering.cpp
  75. RISCVISelLowering.h
  76. RISCVLandingPadSetup.cpp
  77. RISCVLoadStoreOptimizer.cpp
  78. RISCVMachineFunctionInfo.cpp
  79. RISCVMachineFunctionInfo.h
  80. RISCVMacroFusion.td
  81. RISCVMakeCompressible.cpp
  82. RISCVMergeBaseOffset.cpp
  83. RISCVMoveMerger.cpp
  84. RISCVOptWInstrs.cpp
  85. RISCVPfmCounters.td
  86. RISCVPostRAExpandPseudoInsts.cpp
  87. RISCVProcessors.td
  88. RISCVProfiles.td
  89. RISCVPushPopOptimizer.cpp
  90. RISCVRedundantCopyElimination.cpp
  91. RISCVRegisterInfo.cpp
  92. RISCVRegisterInfo.h
  93. RISCVRegisterInfo.td
  94. RISCVSchedGenericOOO.td
  95. RISCVSchedMIPSP8700.td
  96. RISCVSchedRocket.td
  97. RISCVSchedSiFive7.td
  98. RISCVSchedSiFiveP400.td
  99. RISCVSchedSiFiveP500.td
  100. RISCVSchedSiFiveP600.td
  101. RISCVSchedSyntacoreSCR1.td
  102. RISCVSchedSyntacoreSCR345.td
  103. RISCVSchedSyntacoreSCR7.td
  104. RISCVSchedTTAscalonD8.td
  105. RISCVSchedule.td
  106. RISCVScheduleV.td
  107. RISCVScheduleXSf.td
  108. RISCVScheduleZb.td
  109. RISCVScheduleZvk.td
  110. RISCVSchedXiangShanNanHu.td
  111. RISCVSelectionDAGInfo.cpp
  112. RISCVSelectionDAGInfo.h
  113. RISCVSubtarget.cpp
  114. RISCVSubtarget.h
  115. RISCVSystemOperands.td
  116. RISCVTargetMachine.cpp
  117. RISCVTargetMachine.h
  118. RISCVTargetObjectFile.cpp
  119. RISCVTargetObjectFile.h
  120. RISCVTargetTransformInfo.cpp
  121. RISCVTargetTransformInfo.h
  122. RISCVVectorMaskDAGMutation.cpp
  123. RISCVVectorPeephole.cpp
  124. RISCVVLOptimizer.cpp
  125. RISCVVMV0Elimination.cpp
  126. RISCVZacasABIFix.cpp