)]}'
{
  "commit": "070b3e99ac751c9e6cb38201e0eec68d72a55542",
  "tree": "b798e5d2717b69aa89cccd322f5518d37f9e47c0",
  "parents": [
    "12d1aa0c8430c9d8015bfb285aae7d5e260db8ad"
  ],
  "author": {
    "name": "Christudasan Devadasan",
    "email": "Christudasan.Devadasan@amd.com",
    "time": "Thu Jan 08 07:53:18 2026 +0000"
  },
  "committer": {
    "name": "Christudasan Devadasan",
    "email": "Christudasan.Devadasan@amd.com",
    "time": "Tue Jan 13 03:50:24 2026 +0000"
  },
  "message": "[InlineSpiller][AMDGPU] Implement subreg reload during RA spill\n\nCurrently, when a virtual register is partially used, the\nentire tuple is restored from the spilled location, even if\nonly a subset of its sub-registers is needed. This patch\nintroduces support for partial reloads by analyzing actual\nregister usage and restoring only the required sub-registers.\nThis improvement enhances register allocation efficiency,\nparticularly for cases involving tuple virtual registers.\nFor AMDGPU, this change brings considerable improvements\nin workloads that involve matrix operations, large vectors,\nand complex control flows.\n",
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