; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s

target triple = "aarch64"

; Expected to transform
define <vscale x 4 x float> @complex_mul_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
; CHECK-LABEL: complex_mul_v4f32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v2.2d, #0000000000000000
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    fcmla z2.s, p0/m, z1.s, z0.s, #0
; CHECK-NEXT:    fcmla z2.s, p0/m, z1.s, z0.s, #90
; CHECK-NEXT:    mov z0.d, z2.d
; CHECK-NEXT:    ret
entry:
  %a.deinterleaved = tail call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %a)
  %a.real = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } %a.deinterleaved, 0
  %a.imag = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } %a.deinterleaved, 1
  %b.deinterleaved = tail call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %b)
  %b.real = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } %b.deinterleaved, 0
  %b.imag = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } %b.deinterleaved, 1
  %0 = fmul fast <vscale x 2 x float> %b.imag, %a.real
  %1 = fmul fast <vscale x 2 x float> %b.real, %a.imag
  %2 = fadd fast <vscale x 2 x float> %1, %0
  %3 = fmul fast <vscale x 2 x float> %b.real, %a.real
  %4 = fmul fast <vscale x 2 x float> %a.imag, %b.imag
  %5 = fsub fast <vscale x 2 x float> %3, %4
  %interleaved.vec = tail call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %5, <vscale x 2 x float> %2)
  ret <vscale x 4 x float> %interleaved.vec
}

; Expected to transform
define <vscale x 8 x float> @complex_mul_v8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b) {
; CHECK-LABEL: complex_mul_v8f32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v4.2d, #0000000000000000
; CHECK-NEXT:    movi v5.2d, #0000000000000000
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    fcmla z5.s, p0/m, z2.s, z0.s, #0
; CHECK-NEXT:    fcmla z4.s, p0/m, z3.s, z1.s, #0
; CHECK-NEXT:    fcmla z5.s, p0/m, z2.s, z0.s, #90
; CHECK-NEXT:    fcmla z4.s, p0/m, z3.s, z1.s, #90
; CHECK-NEXT:    mov z0.d, z5.d
; CHECK-NEXT:    mov z1.d, z4.d
; CHECK-NEXT:    ret
entry:
  %a.deinterleaved = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %a)
  %a.real = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %a.deinterleaved, 0
  %a.imag = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %a.deinterleaved, 1
  %b.deinterleaved = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %b)
  %b.real = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %b.deinterleaved, 0
  %b.imag = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %b.deinterleaved, 1
  %0 = fmul fast <vscale x 4 x float> %b.imag, %a.real
  %1 = fmul fast <vscale x 4 x float> %b.real, %a.imag
  %2 = fadd fast <vscale x 4 x float> %1, %0
  %3 = fmul fast <vscale x 4 x float> %b.real, %a.real
  %4 = fmul fast <vscale x 4 x float> %a.imag, %b.imag
  %5 = fsub fast <vscale x 4 x float> %3, %4
  %interleaved.vec = tail call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %5, <vscale x 4 x float> %2)
  ret <vscale x 8 x float> %interleaved.vec
}

; Expected to transform
define <vscale x 16 x float> @complex_mul_v16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b) {
; CHECK-LABEL: complex_mul_v16f32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v24.2d, #0000000000000000
; CHECK-NEXT:    movi v25.2d, #0000000000000000
; CHECK-NEXT:    movi v26.2d, #0000000000000000
; CHECK-NEXT:    movi v27.2d, #0000000000000000
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    fcmla z24.s, p0/m, z4.s, z0.s, #0
; CHECK-NEXT:    fcmla z25.s, p0/m, z5.s, z1.s, #0
; CHECK-NEXT:    fcmla z27.s, p0/m, z6.s, z2.s, #0
; CHECK-NEXT:    fcmla z26.s, p0/m, z7.s, z3.s, #0
; CHECK-NEXT:    fcmla z24.s, p0/m, z4.s, z0.s, #90
; CHECK-NEXT:    fcmla z25.s, p0/m, z5.s, z1.s, #90
; CHECK-NEXT:    fcmla z27.s, p0/m, z6.s, z2.s, #90
; CHECK-NEXT:    fcmla z26.s, p0/m, z7.s, z3.s, #90
; CHECK-NEXT:    mov z0.d, z24.d
; CHECK-NEXT:    mov z1.d, z25.d
; CHECK-NEXT:    mov z2.d, z27.d
; CHECK-NEXT:    mov z3.d, z26.d
; CHECK-NEXT:    ret
entry:
  %a.deinterleaved = tail call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.vector.deinterleave2.nxv16f32(<vscale x 16 x float> %a)
  %a.real = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } %a.deinterleaved, 0
  %a.imag = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } %a.deinterleaved, 1
  %b.deinterleaved = tail call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.vector.deinterleave2.nxv16f32(<vscale x 16 x float> %b)
  %b.real = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } %b.deinterleaved, 0
  %b.imag = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } %b.deinterleaved, 1
  %0 = fmul fast <vscale x 8 x float> %b.imag, %a.real
  %1 = fmul fast <vscale x 8 x float> %b.real, %a.imag
  %2 = fadd fast <vscale x 8 x float> %1, %0
  %3 = fmul fast <vscale x 8 x float> %b.real, %a.real
  %4 = fmul fast <vscale x 8 x float> %a.imag, %b.imag
  %5 = fsub fast <vscale x 8 x float> %3, %4
  %interleaved.vec = tail call <vscale x 16 x float> @llvm.vector.interleave2.nxv16f32(<vscale x 8 x float> %5, <vscale x 8 x float> %2)
  ret <vscale x 16 x float> %interleaved.vec
}

declare { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float>)
declare <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float>, <vscale x 2 x float>)

declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
declare <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float>, <vscale x 4 x float>)

declare { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.vector.deinterleave2.nxv16f32(<vscale x 16 x float>)
declare <vscale x 16 x float> @llvm.vector.interleave2.nxv16f32(<vscale x 8 x float>, <vscale x 8 x float>)