| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| |
| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s |
| |
| define <3 x float> @bitcast_v3i32_to_v3f32(<3 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i32_to_v3f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB0_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB0_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i32_to_v3f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i32_to_v3f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i32_to_v3f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i32> %a, splat (i32 3) |
| %a2 = bitcast <3 x i32> %a1 to <3 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i32> %a to <3 x float> |
| br label %end |
| |
| end: |
| %phi = phi <3 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x float> %phi |
| } |
| |
| define <3 x i32> @bitcast_v3f32_to_v3i32(<3 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f32_to_v3i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB1_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB1_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f32_to_v3i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f32_to_v3i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f32_to_v3i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <3 x float> %a1 to <3 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x float> %a to <3 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i32> %phi |
| } |
| |
| define <12 x i8> @bitcast_v3i32_to_v12i8(<3 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i32_to_v12i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_4 |
| ; GCN-NEXT: .LBB2_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB2_3: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v11, s4, v8, 24 |
| ; GCN-NEXT: v_alignbit_b32 v10, s4, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 8 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB2_2 |
| ; GCN-NEXT: .LBB2_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_alignbit_b32 v11, s4, v8, 24 |
| ; GCN-NEXT: v_alignbit_b32 v10, s4, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i32_to_v12i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v8, v2 |
| ; VI-NEXT: v_mov_b32_e32 v14, v1 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr9 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr11 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB2_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; VI-NEXT: .LBB2_2: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB2_4 |
| ; VI-NEXT: ; %bb.3: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14 |
| ; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; VI-NEXT: .LBB2_4: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: v_mov_b32_e32 v0, v13 |
| ; VI-NEXT: v_mov_b32_e32 v4, v14 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i32_to_v12i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v8, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr9 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr11 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB2_2: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB2_4 |
| ; GFX9-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v8, 3, v8 |
| ; GFX9-NEXT: v_add_u32_e32 v14, 3, v14 |
| ; GFX9-NEXT: v_add_u32_e32 v13, 3, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB2_4: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX9-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i32_to_v12i8: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: ; implicit-def: $vgpr9 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr11 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB2_2: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB2_4 |
| ; GFX11-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB2_4: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX11-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i32> %a, splat (i32 3) |
| %a2 = bitcast <3 x i32> %a1 to <12 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i32> %a to <12 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i8> %phi |
| } |
| |
| define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i8_to_v3i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v14, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 24, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 8, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 8, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 24, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_4 |
| ; GCN-NEXT: .LBB3_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB3_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xff, v10 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v7, v8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GCN-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB3_2 |
| ; GCN-NEXT: .LBB3_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v13 |
| ; GCN-NEXT: s_movk_i32 s6, 0x300 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v14 |
| ; GCN-NEXT: s_mov_b32 s7, 0x3000000 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v10 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v15, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_or_b32_e32 v6, v9, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x300, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v7, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v2, v5, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i8_to_v3i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v14, v2 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v3 |
| ; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v5 |
| ; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v7 |
| ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v9 |
| ; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v11 |
| ; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB3_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB3_4 |
| ; VI-NEXT: .LBB3_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB3_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr13 |
| ; VI-NEXT: ; implicit-def: $vgpr14 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr8 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr16 |
| ; VI-NEXT: ; implicit-def: $vgpr15 |
| ; VI-NEXT: ; implicit-def: $vgpr12 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB3_2 |
| ; VI-NEXT: .LBB3_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; VI-NEXT: v_or_b32_sdwa v0, v16, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v6 |
| ; VI-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v4 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v8 |
| ; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v10 |
| ; VI-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v4, 0x300, v4 |
| ; VI-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v4, v2 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i8_to_v3i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v3 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v5 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v9 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v11 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB3_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB3_4 |
| ; GFX9-NEXT: .LBB3_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB3_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr13 |
| ; GFX9-NEXT: ; implicit-def: $vgpr14 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr8 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr16 |
| ; GFX9-NEXT: ; implicit-def: $vgpr15 |
| ; GFX9-NEXT: ; implicit-def: $vgpr12 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB3_2 |
| ; GFX9-NEXT: .LBB3_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v16, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v6 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v8 |
| ; GFX9-NEXT: v_add_u16_e32 v4, 3, v10 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2 |
| ; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i8_to_v3i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 |
| ; GFX11-NEXT: v_lshlrev_b16 v16, 8, v1 |
| ; GFX11-NEXT: v_lshlrev_b16 v12, 8, v3 |
| ; GFX11-NEXT: v_lshlrev_b16 v15, 8, v5 |
| ; GFX11-NEXT: v_lshlrev_b16 v7, 8, v7 |
| ; GFX11-NEXT: v_lshlrev_b16 v3, 8, v9 |
| ; GFX11-NEXT: v_lshlrev_b16 v5, 8, v11 |
| ; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB3_3 |
| ; GFX11-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB3_4 |
| ; GFX11-NEXT: .LBB3_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-NEXT: .LBB3_3: ; %cmp.false |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v8 |
| ; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v10 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v16 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v1, v12 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v2, v15 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v4, v7 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v6, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v8, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr13 |
| ; GFX11-NEXT: ; implicit-def: $vgpr14 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr8 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr16 |
| ; GFX11-NEXT: ; implicit-def: $vgpr12 |
| ; GFX11-NEXT: ; implicit-def: $vgpr15 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v4 |
| ; GFX11-NEXT: ; implicit-def: $vgpr4 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v3, v5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB3_2 |
| ; GFX11-NEXT: .LBB3_4: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u16 v0, v13, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v1, v14, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v2, v4, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, v6, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v6, v8, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v8, v10, 3 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v16, v0 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v15, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v7, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v3, v6 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v5, v8 |
| ; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2 |
| ; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4 |
| ; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3 |
| ; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v3, v5 |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i8> %a, splat (i8 3) |
| %a2 = bitcast <12 x i8> %a1 to <3 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i8> %a to <3 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i32> %phi |
| } |
| |
| define <6 x bfloat> @bitcast_v3i32_to_v6bf16(<3 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i32_to_v6bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB4_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB4_4 |
| ; GCN-NEXT: .LBB4_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB4_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v8 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v7 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB4_2 |
| ; GCN-NEXT: .LBB4_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v8 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i32_to_v6bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i32_to_v6bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i32_to_v6bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i32> %a, splat (i32 3) |
| %a2 = bitcast <3 x i32> %a1 to <6 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i32> %a to <6 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <6 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x bfloat> %phi |
| } |
| |
| define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6bf16_to_v3i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 |
| ; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_4 |
| ; GCN-NEXT: .LBB5_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB5_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v5 |
| ; GCN-NEXT: v_alignbit_b32 v0, v0, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v1, v6, 16 |
| ; GCN-NEXT: v_alignbit_b32 v2, v2, v3, 16 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB5_2 |
| ; GCN-NEXT: .LBB5_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v8 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v9 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v6 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v2, 16 |
| ; GCN-NEXT: v_alignbit_b32 v2, v5, v3, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6bf16_to_v3i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB5_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 |
| ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v2, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 |
| ; VI-NEXT: v_alignbit_b32 v2, v2, v3, 16 |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_alignbit_b32 v1, v1, v3, 16 |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16 |
| ; VI-NEXT: .LBB5_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6bf16_to_v3i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB5_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v2, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v2, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v2 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc |
| ; GFX9-NEXT: s_mov_b32 s7, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7 |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc |
| ; GFX9-NEXT: v_perm_b32 v1, v3, v1, s7 |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; GFX9-NEXT: v_perm_b32 v0, v3, v0, s7 |
| ; GFX9-NEXT: .LBB5_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6bf16_to_v3i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB5_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2 |
| ; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v3 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 |
| ; GFX11-NEXT: v_bfe_u32 v7, v2, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v2 |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_add3_u32 v7, v7, v2, 0x7fff |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo |
| ; GFX11-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) |
| ; GFX11-NEXT: v_bfe_u32 v10, v4, 16, 1 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo |
| ; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 |
| ; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v6, v10, v4, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x7060302 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: v_add3_u32 v7, v8, v1, 0x7fff |
| ; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v1 |
| ; GFX11-NEXT: v_bfe_u32 v9, v5, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v5 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 |
| ; GFX11-NEXT: v_add3_u32 v9, v9, v5, 0x7fff |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10 |
| ; GFX11-NEXT: v_bfe_u32 v6, v0, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v0 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v0, 0x7fff |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v11, vcc_lo |
| ; GFX11-NEXT: v_perm_b32 v1, v4, v1, 0x7060302 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_perm_b32 v0, v5, v0, 0x7060302 |
| ; GFX11-NEXT: .LBB5_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <6 x bfloat> %a1 to <3 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x bfloat> %a to <3 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i32> %phi |
| } |
| |
| define <6 x half> @bitcast_v3i32_to_v6f16(<3 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i32_to_v6f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB6_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB6_4 |
| ; GCN-NEXT: .LBB6_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB6_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v6 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB6_2 |
| ; GCN-NEXT: .LBB6_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i32_to_v6f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i32_to_v6f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i32_to_v6f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i32> %a, splat (i32 3) |
| %a2 = bitcast <3 x i32> %a1 to <6 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i32> %a to <6 x half> |
| br label %end |
| |
| end: |
| %phi = phi <6 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x half> %phi |
| } |
| |
| define <3 x i32> @bitcast_v6f16_to_v3i32(<6 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f16_to_v3i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_4 |
| ; GCN-NEXT: .LBB7_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB7_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v5 |
| ; GCN-NEXT: v_or_b32_e32 v0, v7, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v6, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB7_2 |
| ; GCN-NEXT: .LBB7_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v4, v2 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v5 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f16_to_v3i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB7_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v4, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v4 |
| ; VI-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v4 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v3 |
| ; VI-NEXT: .LBB7_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f16_to_v3i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f16_to_v3i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <6 x half> %a1 to <3 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x half> %a to <3 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i32> %phi |
| } |
| |
| define <6 x i16> @bitcast_v3i32_to_v6i16(<3 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i32_to_v6i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB8_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB8_4 |
| ; GCN-NEXT: .LBB8_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB8_3: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v5, s4, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB8_2 |
| ; GCN-NEXT: .LBB8_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, s4, v4, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i32_to_v6i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i32_to_v6i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i32_to_v6i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i32> %a, splat (i32 3) |
| %a2 = bitcast <3 x i32> %a1 to <6 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i32> %a to <6 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i16> %phi |
| } |
| |
| define <3 x i32> @bitcast_v6i16_to_v3i32(<6 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i16_to_v3i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB9_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB9_4 |
| ; GCN-NEXT: .LBB9_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB9_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v6 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB9_2 |
| ; GCN-NEXT: .LBB9_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v4 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v6, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v5, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i16_to_v3i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB9_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v4, 3 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v3, v0 |
| ; VI-NEXT: .LBB9_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i16_to_v3i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i16_to_v3i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i16> %a, splat (i16 3) |
| %a2 = bitcast <6 x i16> %a1 to <3 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i16> %a to <3 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i32> %phi |
| } |
| |
| define <12 x i8> @bitcast_v3f32_to_v12i8(<3 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f32_to_v12i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB10_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB10_4 |
| ; GCN-NEXT: .LBB10_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB10_3: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v11, s4, v8, 24 |
| ; GCN-NEXT: v_alignbit_b32 v10, s4, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 8 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB10_2 |
| ; GCN-NEXT: .LBB10_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_alignbit_b32 v11, s4, v8, 24 |
| ; GCN-NEXT: v_alignbit_b32 v10, s4, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f32_to_v12i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v8, v2 |
| ; VI-NEXT: v_mov_b32_e32 v14, v1 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr9 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr11 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB10_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; VI-NEXT: .LBB10_2: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB10_4 |
| ; VI-NEXT: ; %bb.3: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; VI-NEXT: v_add_f32_e32 v14, 1.0, v14 |
| ; VI-NEXT: v_add_f32_e32 v13, 1.0, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; VI-NEXT: .LBB10_4: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: v_mov_b32_e32 v0, v13 |
| ; VI-NEXT: v_mov_b32_e32 v4, v14 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f32_to_v12i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v8, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr9 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr11 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB10_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB10_2: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB10_4 |
| ; GFX9-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14 |
| ; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB10_4: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX9-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f32_to_v12i8: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: ; implicit-def: $vgpr9 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr11 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB10_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB10_2: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB10_4 |
| ; GFX11-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX11-NEXT: v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v13, 1.0, v13 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB10_4: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX11-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <3 x float> %a1 to <12 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x float> %a to <12 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i8> %phi |
| } |
| |
| define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i8_to_v3f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v14, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 24, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 8, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 8, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 24, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GCN-NEXT: .LBB11_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB11_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xff, v10 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v7, v8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GCN-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB11_2 |
| ; GCN-NEXT: .LBB11_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v13 |
| ; GCN-NEXT: s_movk_i32 s6, 0x300 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v14 |
| ; GCN-NEXT: s_mov_b32 s7, 0x3000000 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v10 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xff, v8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v15, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_or_b32_e32 v6, v9, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x300, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v7, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v2, v5, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i8_to_v3f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v14, v2 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v3 |
| ; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v5 |
| ; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v7 |
| ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v9 |
| ; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v11 |
| ; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB11_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB11_4 |
| ; VI-NEXT: .LBB11_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB11_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr13 |
| ; VI-NEXT: ; implicit-def: $vgpr14 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr8 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr16 |
| ; VI-NEXT: ; implicit-def: $vgpr15 |
| ; VI-NEXT: ; implicit-def: $vgpr12 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB11_2 |
| ; VI-NEXT: .LBB11_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; VI-NEXT: v_or_b32_sdwa v0, v16, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v6 |
| ; VI-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v4 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v8 |
| ; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v10 |
| ; VI-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v4, 0x300, v4 |
| ; VI-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v4, v2 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i8_to_v3f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v3 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v5 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v9 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v11 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GFX9-NEXT: .LBB11_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB11_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr13 |
| ; GFX9-NEXT: ; implicit-def: $vgpr14 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr8 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr16 |
| ; GFX9-NEXT: ; implicit-def: $vgpr15 |
| ; GFX9-NEXT: ; implicit-def: $vgpr12 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX9-NEXT: .LBB11_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v16, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v6 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v8 |
| ; GFX9-NEXT: v_add_u16_e32 v4, 3, v10 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2 |
| ; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i8_to_v3f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 |
| ; GFX11-NEXT: v_lshlrev_b16 v16, 8, v1 |
| ; GFX11-NEXT: v_lshlrev_b16 v12, 8, v3 |
| ; GFX11-NEXT: v_lshlrev_b16 v15, 8, v5 |
| ; GFX11-NEXT: v_lshlrev_b16 v7, 8, v7 |
| ; GFX11-NEXT: v_lshlrev_b16 v3, 8, v9 |
| ; GFX11-NEXT: v_lshlrev_b16 v5, 8, v11 |
| ; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GFX11-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GFX11-NEXT: .LBB11_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-NEXT: .LBB11_3: ; %cmp.false |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v8 |
| ; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v10 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v16 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v1, v12 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v2, v15 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v4, v7 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v6, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v8, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr13 |
| ; GFX11-NEXT: ; implicit-def: $vgpr14 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr8 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr16 |
| ; GFX11-NEXT: ; implicit-def: $vgpr12 |
| ; GFX11-NEXT: ; implicit-def: $vgpr15 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v4 |
| ; GFX11-NEXT: ; implicit-def: $vgpr4 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v3, v5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX11-NEXT: .LBB11_4: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u16 v0, v13, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v1, v14, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v2, v4, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, v6, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v6, v8, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v8, v10, 3 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v16, v0 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v15, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v7, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v3, v6 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v5, v8 |
| ; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2 |
| ; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4 |
| ; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3 |
| ; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v3, v5 |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i8> %a, splat (i8 3) |
| %a2 = bitcast <12 x i8> %a1 to <3 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i8> %a to <3 x float> |
| br label %end |
| |
| end: |
| %phi = phi <3 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x float> %phi |
| } |
| |
| define <6 x bfloat> @bitcast_v3f32_to_v6bf16(<3 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f32_to_v6bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB12_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB12_4 |
| ; GCN-NEXT: .LBB12_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB12_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v8 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v7 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB12_2 |
| ; GCN-NEXT: .LBB12_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v7 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v8 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f32_to_v6bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f32_to_v6bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f32_to_v6bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <3 x float> %a1 to <6 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x float> %a to <6 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <6 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x bfloat> %phi |
| } |
| |
| define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6bf16_to_v3f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 |
| ; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB13_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB13_4 |
| ; GCN-NEXT: .LBB13_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB13_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v5 |
| ; GCN-NEXT: v_alignbit_b32 v0, v0, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v1, v6, 16 |
| ; GCN-NEXT: v_alignbit_b32 v2, v2, v3, 16 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB13_2 |
| ; GCN-NEXT: .LBB13_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v8 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v9 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v6 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v2, 16 |
| ; GCN-NEXT: v_alignbit_b32 v2, v5, v3, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6bf16_to_v3f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB13_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 |
| ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v2, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 |
| ; VI-NEXT: v_alignbit_b32 v2, v2, v3, 16 |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_alignbit_b32 v1, v1, v3, 16 |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16 |
| ; VI-NEXT: .LBB13_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6bf16_to_v3f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB13_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v2, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v2, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v2 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc |
| ; GFX9-NEXT: s_mov_b32 s7, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7 |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc |
| ; GFX9-NEXT: v_perm_b32 v1, v3, v1, s7 |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; GFX9-NEXT: v_perm_b32 v0, v3, v0, s7 |
| ; GFX9-NEXT: .LBB13_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6bf16_to_v3f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB13_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2 |
| ; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v3 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 |
| ; GFX11-NEXT: v_bfe_u32 v7, v2, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v2 |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_add3_u32 v7, v7, v2, 0x7fff |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo |
| ; GFX11-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) |
| ; GFX11-NEXT: v_bfe_u32 v10, v4, 16, 1 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo |
| ; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 |
| ; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v6, v10, v4, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x7060302 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: v_add3_u32 v7, v8, v1, 0x7fff |
| ; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v1 |
| ; GFX11-NEXT: v_bfe_u32 v9, v5, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v5 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 |
| ; GFX11-NEXT: v_add3_u32 v9, v9, v5, 0x7fff |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10 |
| ; GFX11-NEXT: v_bfe_u32 v6, v0, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v0 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v0, 0x7fff |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v11, vcc_lo |
| ; GFX11-NEXT: v_perm_b32 v1, v4, v1, 0x7060302 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_perm_b32 v0, v5, v0, 0x7060302 |
| ; GFX11-NEXT: .LBB13_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <6 x bfloat> %a1 to <3 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x bfloat> %a to <3 x float> |
| br label %end |
| |
| end: |
| %phi = phi <3 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x float> %phi |
| } |
| |
| define <6 x half> @bitcast_v3f32_to_v6f16(<3 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f32_to_v6f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB14_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB14_4 |
| ; GCN-NEXT: .LBB14_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB14_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v6 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB14_2 |
| ; GCN-NEXT: .LBB14_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v7 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f32_to_v6f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f32_to_v6f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f32_to_v6f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <3 x float> %a1 to <6 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x float> %a to <6 x half> |
| br label %end |
| |
| end: |
| %phi = phi <6 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x half> %phi |
| } |
| |
| define <3 x float> @bitcast_v6f16_to_v3f32(<6 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f16_to_v3f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB15_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB15_4 |
| ; GCN-NEXT: .LBB15_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB15_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v5 |
| ; GCN-NEXT: v_or_b32_e32 v0, v7, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v6, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB15_2 |
| ; GCN-NEXT: .LBB15_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v4, v2 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v5 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f16_to_v3f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB15_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v4, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v4 |
| ; VI-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v4 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v3 |
| ; VI-NEXT: .LBB15_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f16_to_v3f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f16_to_v3f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <6 x half> %a1 to <3 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x half> %a to <3 x float> |
| br label %end |
| |
| end: |
| %phi = phi <3 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x float> %phi |
| } |
| |
| define <6 x i16> @bitcast_v3f32_to_v6i16(<3 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f32_to_v6i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB16_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB16_4 |
| ; GCN-NEXT: .LBB16_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB16_3: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v5, s4, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB16_2 |
| ; GCN-NEXT: .LBB16_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, s4, v4, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f32_to_v6i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f32_to_v6i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f32_to_v6i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <3 x float> %a1 to <6 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x float> %a to <6 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i16> %phi |
| } |
| |
| define <3 x float> @bitcast_v6i16_to_v3f32(<6 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i16_to_v3f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB17_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB17_4 |
| ; GCN-NEXT: .LBB17_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB17_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v6 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB17_2 |
| ; GCN-NEXT: .LBB17_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v4 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v6, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v5, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i16_to_v3f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB17_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v4, 3 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v3, v0 |
| ; VI-NEXT: .LBB17_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i16_to_v3f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i16_to_v3f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i16> %a, splat (i16 3) |
| %a2 = bitcast <6 x i16> %a1 to <3 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i16> %a to <3 x float> |
| br label %end |
| |
| end: |
| %phi = phi <3 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x float> %phi |
| } |
| |
| define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i8_to_v6bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v14, 24, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 8, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB18_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 24, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xff, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v9 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xff, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v11, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v13, v14, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v3 |
| ; GCN-NEXT: v_or_b32_e32 v3, v15, v4 |
| ; GCN-NEXT: v_or_b32_e32 v12, v6, v5 |
| ; GCN-NEXT: v_or_b32_e32 v5, v16, v8 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: .LBB18_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB18_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 8, v9 |
| ; GCN-NEXT: s_movk_i32 s6, 0x300 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v10 |
| ; GCN-NEXT: s_mov_b32 s7, 0x3000000 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 8, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v4, v17, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x300, v3 |
| ; GCN-NEXT: v_or_b32_e32 v3, v16, v5 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v15, v6 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v14, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s7, v2 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v3 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0 |
| ; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v0 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v1 |
| ; GCN-NEXT: .LBB18_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v0, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v1, v13 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v12 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i8_to_v6bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v14, v2 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v3 |
| ; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v5 |
| ; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v7 |
| ; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v9 |
| ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v11 |
| ; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB18_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB18_4 |
| ; VI-NEXT: .LBB18_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB18_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v3, v10, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr13 |
| ; VI-NEXT: ; implicit-def: $vgpr14 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr8 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr17 |
| ; VI-NEXT: ; implicit-def: $vgpr16 |
| ; VI-NEXT: ; implicit-def: $vgpr15 |
| ; VI-NEXT: ; implicit-def: $vgpr12 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB18_2 |
| ; VI-NEXT: .LBB18_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; VI-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v6 |
| ; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v3, v12, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v8 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v10 |
| ; VI-NEXT: v_or_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v3, 0x300, v3 |
| ; VI-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i8_to_v6bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v3 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v5 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v7 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v9 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v11 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB18_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB18_4 |
| ; GFX9-NEXT: .LBB18_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB18_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v10, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr13 |
| ; GFX9-NEXT: ; implicit-def: $vgpr14 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr8 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr17 |
| ; GFX9-NEXT: ; implicit-def: $vgpr16 |
| ; GFX9-NEXT: ; implicit-def: $vgpr15 |
| ; GFX9-NEXT: ; implicit-def: $vgpr12 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB18_2 |
| ; GFX9-NEXT: .LBB18_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v6 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v12, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v8 |
| ; GFX9-NEXT: v_add_u16_e32 v3, 3, v10 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2 |
| ; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i8_to_v6bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 |
| ; GFX11-NEXT: v_lshlrev_b16 v17, 8, v1 |
| ; GFX11-NEXT: v_lshlrev_b16 v15, 8, v3 |
| ; GFX11-NEXT: v_lshlrev_b16 v16, 8, v5 |
| ; GFX11-NEXT: v_lshlrev_b16 v12, 8, v7 |
| ; GFX11-NEXT: v_lshlrev_b16 v5, 8, v9 |
| ; GFX11-NEXT: v_lshlrev_b16 v7, 8, v11 |
| ; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB18_3 |
| ; GFX11-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB18_4 |
| ; GFX11-NEXT: .LBB18_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-NEXT: .LBB18_3: ; %cmp.false |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v10 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v17 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v1, v15 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v2, v16 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v3, v12 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v6, v7 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr13 |
| ; GFX11-NEXT: ; implicit-def: $vgpr14 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr8 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr17 |
| ; GFX11-NEXT: ; implicit-def: $vgpr15 |
| ; GFX11-NEXT: ; implicit-def: $vgpr16 |
| ; GFX11-NEXT: ; implicit-def: $vgpr12 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr4 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB18_2 |
| ; GFX11-NEXT: .LBB18_4: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u16 v0, v13, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v1, v14, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v2, v4, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v3, v6, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, v8, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v6, v10, 3 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v17, v0 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v15, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v16, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v7, v6 |
| ; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2 |
| ; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4 |
| ; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i8> %a, splat (i8 3) |
| %a2 = bitcast <12 x i8> %a1 to <6 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i8> %a to <6 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <6 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x bfloat> %phi |
| } |
| |
| define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6bf16_to_v12i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v5 |
| ; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB19_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB19_4 |
| ; GCN-NEXT: .LBB19_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB19_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v17 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 24, v13 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; GCN-NEXT: v_alignbit_b32 v0, v0, v15, 16 |
| ; GCN-NEXT: v_alignbit_b32 v4, v6, v14, 16 |
| ; GCN-NEXT: v_alignbit_b32 v8, v10, v12, 16 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB19_2 |
| ; GCN-NEXT: .LBB19_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v15 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v17 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v14 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v16 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v12 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v13 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x40c00000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v11, 0x40c00000, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v3 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v4, v6, v2, 16 |
| ; GCN-NEXT: v_alignbit_b32 v8, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 24, v11 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6bf16_to_v12i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v13, v2 |
| ; VI-NEXT: v_mov_b32_e32 v16, v1 |
| ; VI-NEXT: v_mov_b32_e32 v15, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr9 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr11 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB19_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v15 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[15:16] |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v15 |
| ; VI-NEXT: .LBB19_2: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB19_4 |
| ; VI-NEXT: ; %bb.3: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v16 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 |
| ; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_alignbit_b32 v16, v1, v0, 16 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v15 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1 |
| ; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_alignbit_b32 v15, v1, v0, 16 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v13 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1 |
| ; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v13 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_alignbit_b32 v13, v1, v0, 16 |
| ; VI-NEXT: v_mov_b32_e32 v14, 0x7fc07fc0 |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[15:16] |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v13 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v15 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v15 |
| ; VI-NEXT: .LBB19_4: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: v_mov_b32_e32 v0, v15 |
| ; VI-NEXT: v_mov_b32_e32 v4, v16 |
| ; VI-NEXT: v_mov_b32_e32 v8, v13 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6bf16_to_v12i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v8, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr9 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr11 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB19_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB19_2: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB19_4 |
| ; GFX9-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v14 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_add3_u32 v1, v1, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v14 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc |
| ; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v1, v1, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v13 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v13 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v5, v5, v4, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc |
| ; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GFX9-NEXT: v_bfe_u32 v6, v5, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v6, v6, v5, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v7, 0x400000, v5 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 |
| ; GFX9-NEXT: v_bfe_u32 v7, v6, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v7, v7, v6, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v8, 0x400000, v6 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 |
| ; GFX9-NEXT: s_mov_b32 s7, 0x7060302 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc |
| ; GFX9-NEXT: v_perm_b32 v1, v2, v3, s7 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s7 |
| ; GFX9-NEXT: v_perm_b32 v11, v5, v7, s7 |
| ; GFX9-NEXT: v_mov_b32_e32 v12, 0x7fc07fc0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v3 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v4 |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v11 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v11 |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v2 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v7 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v1 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: .LBB19_4: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX9-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6bf16_to_v12i8: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: ; implicit-def: $vgpr9 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr11 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB19_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB19_2: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB19_4 |
| ; GFX11-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v14 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v8 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v13 |
| ; GFX11-NEXT: v_dual_mov_b32 v12, 0x7fc07fc0 :: v_dual_lshlrev_b32 v3, 16, v13 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX11-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v2, 0x40c00000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_bfe_u32 v7, v1, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v8 |
| ; GFX11-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX11-NEXT: v_add3_u32 v7, v7, v1, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v14 |
| ; GFX11-NEXT: v_bfe_u32 v10, v2, 16, 1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX11-NEXT: v_bfe_u32 v6, v0, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v0, 0x7fff |
| ; GFX11-NEXT: v_add_f32_e32 v0, 0x40c00000, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: v_add3_u32 v1, v10, v2, 0x7fff |
| ; GFX11-NEXT: v_bfe_u32 v8, v3, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v0 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-NEXT: v_bfe_u32 v9, v0, 16, 1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v7 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v2, v1, v4, vcc_lo |
| ; GFX11-NEXT: v_add3_u32 v4, v8, v3, 0x7fff |
| ; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v3 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 |
| ; GFX11-NEXT: v_bfe_u32 v1, v5, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v9, v9, v0, 0x7fff |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: v_add3_u32 v1, v1, v5, 0x7fff |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_perm_b32 v0, v2, v3, 0x7060302 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v3 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v11, vcc_lo |
| ; GFX11-NEXT: v_perm_b32 v1, v6, v7, 0x7060302 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v6 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_perm_b32 v11, v4, v5, 0x7060302 |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v5 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v1 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v1 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v11 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v11 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-NEXT: .LBB19_4: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX11-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <6 x bfloat> %a1 to <12 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x bfloat> %a to <12 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i8> %phi |
| } |
| |
| define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i8_to_v6f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v13, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v14, 8, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 8, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 8, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v16, 8, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 8, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB20_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v14 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v15 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v7 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v16 |
| ; GCN-NEXT: v_or_b32_e32 v5, v5, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: .LBB20_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB20_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v10 |
| ; GCN-NEXT: s_movk_i32 s6, 0x300 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v13 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5 |
| ; GCN-NEXT: v_or_b32_e32 v0, v17, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v3, v7, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v15, v4 |
| ; GCN-NEXT: v_or_b32_e32 v2, v14, v2 |
| ; GCN-NEXT: v_or_b32_e32 v5, v12, v5 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 0x300, v0 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x300, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v6 |
| ; GCN-NEXT: .LBB20_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v2, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v9 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i8_to_v6f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v14, v2 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v3 |
| ; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v5 |
| ; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v7 |
| ; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v9 |
| ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v11 |
| ; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB20_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB20_4 |
| ; VI-NEXT: .LBB20_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB20_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v3, v10, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr13 |
| ; VI-NEXT: ; implicit-def: $vgpr14 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr8 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr17 |
| ; VI-NEXT: ; implicit-def: $vgpr16 |
| ; VI-NEXT: ; implicit-def: $vgpr15 |
| ; VI-NEXT: ; implicit-def: $vgpr12 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB20_2 |
| ; VI-NEXT: .LBB20_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; VI-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v6 |
| ; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v3, v12, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v8 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v10 |
| ; VI-NEXT: v_or_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v3, 0x300, v3 |
| ; VI-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i8_to_v6f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v3 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v5 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v7 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v9 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v11 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB20_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB20_4 |
| ; GFX9-NEXT: .LBB20_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB20_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v10, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr13 |
| ; GFX9-NEXT: ; implicit-def: $vgpr14 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr8 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr17 |
| ; GFX9-NEXT: ; implicit-def: $vgpr16 |
| ; GFX9-NEXT: ; implicit-def: $vgpr15 |
| ; GFX9-NEXT: ; implicit-def: $vgpr12 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB20_2 |
| ; GFX9-NEXT: .LBB20_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v6 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v12, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v8 |
| ; GFX9-NEXT: v_add_u16_e32 v3, 3, v10 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2 |
| ; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i8_to_v6f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 |
| ; GFX11-NEXT: v_lshlrev_b16 v17, 8, v1 |
| ; GFX11-NEXT: v_lshlrev_b16 v15, 8, v3 |
| ; GFX11-NEXT: v_lshlrev_b16 v16, 8, v5 |
| ; GFX11-NEXT: v_lshlrev_b16 v12, 8, v7 |
| ; GFX11-NEXT: v_lshlrev_b16 v5, 8, v9 |
| ; GFX11-NEXT: v_lshlrev_b16 v7, 8, v11 |
| ; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB20_3 |
| ; GFX11-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB20_4 |
| ; GFX11-NEXT: .LBB20_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-NEXT: .LBB20_3: ; %cmp.false |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v10 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v17 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v1, v15 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v2, v16 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v3, v12 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v6, v7 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr13 |
| ; GFX11-NEXT: ; implicit-def: $vgpr14 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr8 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr17 |
| ; GFX11-NEXT: ; implicit-def: $vgpr15 |
| ; GFX11-NEXT: ; implicit-def: $vgpr16 |
| ; GFX11-NEXT: ; implicit-def: $vgpr12 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr4 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB20_2 |
| ; GFX11-NEXT: .LBB20_4: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u16 v0, v13, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v1, v14, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v2, v4, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v3, v6, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, v8, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v6, v10, 3 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v17, v0 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v15, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v16, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v7, v6 |
| ; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2 |
| ; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4 |
| ; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i8> %a, splat (i8 3) |
| %a2 = bitcast <12 x i8> %a1 to <6 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i8> %a to <6 x half> |
| br label %end |
| |
| end: |
| %phi = phi <6 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x half> %phi |
| } |
| |
| define <12 x i8> @bitcast_v6f16_to_v12i8(<6 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f16_to_v12i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB21_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB21_4 |
| ; GCN-NEXT: .LBB21_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB21_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v10 |
| ; GCN-NEXT: v_bfe_u32 v7, v6, 8, 8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v14, v0 |
| ; GCN-NEXT: v_or_b32_e32 v4, v13, v1 |
| ; GCN-NEXT: v_or_b32_e32 v8, v12, v2 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GCN-NEXT: v_bfe_u32 v11, v10, 8, 8 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB21_2 |
| ; GCN-NEXT: .LBB21_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v12 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v10 |
| ; GCN-NEXT: v_bfe_u32 v7, v6, 8, 8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v4, v2, v4 |
| ; GCN-NEXT: v_or_b32_e32 v8, v3, v5 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GCN-NEXT: v_bfe_u32 v11, v10, 8, 8 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f16_to_v12i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v8, v2 |
| ; VI-NEXT: v_mov_b32_e32 v14, v1 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr9 |
| ; VI-NEXT: ; implicit-def: $vgpr11 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; VI-NEXT: ; %bb.2: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB21_4 |
| ; VI-NEXT: ; %bb.3: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v6, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6 |
| ; VI-NEXT: v_add_f16_e32 v14, 0x200, v14 |
| ; VI-NEXT: v_add_f16_sdwa v2, v13, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_sdwa v10, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v14, v0 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; VI-NEXT: v_add_f16_e32 v13, 0x200, v13 |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10 |
| ; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 |
| ; VI-NEXT: v_or_b32_e32 v0, v13, v0 |
| ; VI-NEXT: v_or_b32_e32 v11, v8, v3 |
| ; VI-NEXT: v_mov_b32_e32 v12, 0x7e007e00 |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1] |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v11 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12] |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: v_bfe_u32 v7, v6, 8, 8 |
| ; VI-NEXT: .LBB21_4: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: v_mov_b32_e32 v0, v13 |
| ; VI-NEXT: v_mov_b32_e32 v4, v14 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f16_to_v12i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v16, v1 |
| ; GFX9-NEXT: v_mov_b32_e32 v15, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr9 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr11 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v16 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v15 |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[15:16] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v15 |
| ; GFX9-NEXT: .LBB21_2: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB21_4 |
| ; GFX9-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v16, v16, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_mov_b32_e32 v14, 0x7e007e00 |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[15:16] |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v16 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v15 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v15 |
| ; GFX9-NEXT: .LBB21_4: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: v_mov_b32_e32 v0, v15 |
| ; GFX9-NEXT: v_mov_b32_e32 v4, v16 |
| ; GFX9-NEXT: v_mov_b32_e32 v8, v13 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f16_to_v12i8: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v16, v1 |
| ; GFX11-NEXT: v_mov_b32_e32 v15, v0 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: ; implicit-def: $vgpr9 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr11 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v13 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v16 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v15 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[15:16] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v15 |
| ; GFX11-NEXT: .LBB21_2: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB21_4 |
| ; GFX11-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_mov_b32_e32 v14, 0x7e007e00 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v16 |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[15:16] |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v13 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v16 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v16 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v15 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v15 |
| ; GFX11-NEXT: .LBB21_4: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, v15 |
| ; GFX11-NEXT: v_mov_b32_e32 v4, v16 |
| ; GFX11-NEXT: v_mov_b32_e32 v8, v13 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <6 x half> %a1 to <12 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x half> %a to <12 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i8> %phi |
| } |
| |
| define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i8_to_v6i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v14, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v15, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v16, 8, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 24, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 24, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v18, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 8, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB22_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB22_4 |
| ; GCN-NEXT: .LBB22_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB22_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v14 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v15 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xff, v10 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v16 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v18 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v7, v1 |
| ; GCN-NEXT: v_or_b32_e32 v6, v12, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v9, v5 |
| ; GCN-NEXT: v_or_b32_e32 v2, v0, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v3, v6 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v6, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB22_2 |
| ; GCN-NEXT: .LBB22_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v13 |
| ; GCN-NEXT: s_movk_i32 s6, 0x300 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v15 |
| ; GCN-NEXT: s_mov_b32 s7, 0x3000000 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v14 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v10 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5 |
| ; GCN-NEXT: v_or_b32_e32 v0, v18, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v17, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v7, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x300, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v9, v5 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, s7, v0 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v1 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v3 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v4 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i8_to_v6i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v14, v2 |
| ; VI-NEXT: v_mov_b32_e32 v13, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v3 |
| ; VI-NEXT: v_lshlrev_b16_e32 v15, 8, v5 |
| ; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v7 |
| ; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v9 |
| ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v11 |
| ; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB22_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB22_4 |
| ; VI-NEXT: .LBB22_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB22_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v3, v10, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr13 |
| ; VI-NEXT: ; implicit-def: $vgpr14 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr6 |
| ; VI-NEXT: ; implicit-def: $vgpr8 |
| ; VI-NEXT: ; implicit-def: $vgpr10 |
| ; VI-NEXT: ; implicit-def: $vgpr17 |
| ; VI-NEXT: ; implicit-def: $vgpr16 |
| ; VI-NEXT: ; implicit-def: $vgpr15 |
| ; VI-NEXT: ; implicit-def: $vgpr12 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB22_2 |
| ; VI-NEXT: .LBB22_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; VI-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v6 |
| ; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v3, v12, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v8 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v10 |
| ; VI-NEXT: v_or_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_add_u16_e32 v3, 0x300, v3 |
| ; VI-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i8_to_v6i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v3 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v5 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v7 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v9 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v11 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB22_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB22_4 |
| ; GFX9-NEXT: .LBB22_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB22_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v4, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v10, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr13 |
| ; GFX9-NEXT: ; implicit-def: $vgpr14 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr8 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr17 |
| ; GFX9-NEXT: ; implicit-def: $vgpr16 |
| ; GFX9-NEXT: ; implicit-def: $vgpr15 |
| ; GFX9-NEXT: ; implicit-def: $vgpr12 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB22_2 |
| ; GFX9-NEXT: .LBB22_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v13 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v14 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 3, v4 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v6 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v12, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1 |
| ; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v8 |
| ; GFX9-NEXT: v_add_u16_e32 v3, 3, v10 |
| ; GFX9-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2 |
| ; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i8_to_v6i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 |
| ; GFX11-NEXT: v_lshlrev_b16 v17, 8, v1 |
| ; GFX11-NEXT: v_lshlrev_b16 v15, 8, v3 |
| ; GFX11-NEXT: v_lshlrev_b16 v16, 8, v5 |
| ; GFX11-NEXT: v_lshlrev_b16 v12, 8, v7 |
| ; GFX11-NEXT: v_lshlrev_b16 v5, 8, v9 |
| ; GFX11-NEXT: v_lshlrev_b16 v7, 8, v11 |
| ; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB22_3 |
| ; GFX11-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execnz .LBB22_4 |
| ; GFX11-NEXT: .LBB22_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-NEXT: .LBB22_3: ; %cmp.false |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v13 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v14 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v6 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v8 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v10 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v17 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v1, v15 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v2, v16 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v3, v12 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v6, v7 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr13 |
| ; GFX11-NEXT: ; implicit-def: $vgpr14 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr8 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr17 |
| ; GFX11-NEXT: ; implicit-def: $vgpr15 |
| ; GFX11-NEXT: ; implicit-def: $vgpr16 |
| ; GFX11-NEXT: ; implicit-def: $vgpr12 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr4 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB22_2 |
| ; GFX11-NEXT: .LBB22_4: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u16 v0, v13, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v1, v14, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v2, v4, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v3, v6, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, v8, 3 |
| ; GFX11-NEXT: v_add_nc_u16 v6, v10, 3 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4 |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v17, v0 |
| ; GFX11-NEXT: v_or_b32_e32 v1, v15, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v16, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v5, v7, v6 |
| ; GFX11-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-NEXT: v_add_nc_u16 v2, 0x300, v2 |
| ; GFX11-NEXT: v_add_nc_u16 v3, 0x300, v3 |
| ; GFX11-NEXT: v_add_nc_u16 v4, 0x300, v4 |
| ; GFX11-NEXT: v_add_nc_u16 v5, 0x300, v5 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GFX11-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-NEXT: v_or_b32_e32 v2, v4, v5 |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i8> %a, splat (i8 3) |
| %a2 = bitcast <12 x i8> %a1 to <6 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i8> %a to <6 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i16> %phi |
| } |
| |
| define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i16_to_v12i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v15, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v16, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v14, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v16 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v15 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB23_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB23_4 |
| ; GCN-NEXT: .LBB23_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB23_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v14 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v12 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v16 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v15 |
| ; GCN-NEXT: v_bfe_u32 v7, v16, 8, 8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v17 |
| ; GCN-NEXT: v_or_b32_e32 v4, v1, v18 |
| ; GCN-NEXT: v_or_b32_e32 v8, v2, v19 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GCN-NEXT: v_bfe_u32 v11, v15, 8, 8 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB23_2 |
| ; GCN-NEXT: .LBB23_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v14 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v13 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v12 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v17, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v18, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v19, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v2 |
| ; GCN-NEXT: v_alignbit_b32 v3, v4, v0, 24 |
| ; GCN-NEXT: v_alignbit_b32 v2, v4, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v4, v0, 8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 24, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 8, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 24, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i16_to_v12i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2 |
| ; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v0 |
| ; VI-NEXT: ; implicit-def: $vgpr16 |
| ; VI-NEXT: ; implicit-def: $vgpr15 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: ; implicit-def: $vgpr14 |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr7 |
| ; VI-NEXT: ; implicit-def: $vgpr8 |
| ; VI-NEXT: ; implicit-def: $vgpr9 |
| ; VI-NEXT: ; implicit-def: $vgpr11 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB23_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2 |
| ; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v0 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3] |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1] |
| ; VI-NEXT: v_mov_b32_e32 v16, v0 |
| ; VI-NEXT: v_mov_b32_e32 v14, v1 |
| ; VI-NEXT: v_mov_b32_e32 v8, v2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: .LBB23_2: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB23_4 |
| ; VI-NEXT: ; %bb.3: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 3 |
| ; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v13, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v14, 3, v1 |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6 |
| ; VI-NEXT: v_add_u16_e32 v16, 3, v0 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v13 |
| ; VI-NEXT: v_or_b32_e32 v1, v14, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v16, v0 |
| ; VI-NEXT: v_add_u16_sdwa v10, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v8, 3, v2 |
| ; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10 |
| ; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1] |
| ; VI-NEXT: v_or_b32_e32 v2, v8, v2 |
| ; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3] |
| ; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2 |
| ; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v0 |
| ; VI-NEXT: v_bfe_u32 v7, v6, 8, 8 |
| ; VI-NEXT: .LBB23_4: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: v_mov_b32_e32 v0, v16 |
| ; VI-NEXT: v_mov_b32_e32 v1, v15 |
| ; VI-NEXT: v_mov_b32_e32 v2, v13 |
| ; VI-NEXT: v_mov_b32_e32 v4, v14 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i16_to_v12i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v8, v2 |
| ; GFX9-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX9-NEXT: v_mov_b32_e32 v13, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr6 |
| ; GFX9-NEXT: ; implicit-def: $vgpr7 |
| ; GFX9-NEXT: ; implicit-def: $vgpr9 |
| ; GFX9-NEXT: ; implicit-def: $vgpr10 |
| ; GFX9-NEXT: ; implicit-def: $vgpr11 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB23_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB23_2: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB23_4 |
| ; GFX9-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX9-NEXT: .LBB23_4: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX9-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i16_to_v12i8: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0 |
| ; GFX11-NEXT: v_mov_b32_e32 v14, v1 |
| ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-NEXT: ; implicit-def: $vgpr6 |
| ; GFX11-NEXT: ; implicit-def: $vgpr7 |
| ; GFX11-NEXT: ; implicit-def: $vgpr9 |
| ; GFX11-NEXT: ; implicit-def: $vgpr10 |
| ; GFX11-NEXT: ; implicit-def: $vgpr11 |
| ; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB23_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB23_2: ; %Flow |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB23_4 |
| ; GFX11-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v8 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8 |
| ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v14 |
| ; GFX11-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9] |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v14 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13 |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v13 |
| ; GFX11-NEXT: .LBB23_4: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, v13 |
| ; GFX11-NEXT: v_mov_b32_e32 v4, v14 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i16> %a, splat (i16 3) |
| %a2 = bitcast <6 x i16> %a1 to <12 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i16> %a to <12 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i8> %phi |
| } |
| |
| define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6bf16_to_v6f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v4 |
| ; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB24_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB24_4 |
| ; GCN-NEXT: .LBB24_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB24_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB24_2 |
| ; GCN-NEXT: .LBB24_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v11 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v10 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v8 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v6 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6bf16_to_v6f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB24_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v1 |
| ; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5 |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc |
| ; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5 |
| ; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc |
| ; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v2 |
| ; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; VI-NEXT: v_bfe_u32 v6, v5, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6 |
| ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 |
| ; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 |
| ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc |
| ; VI-NEXT: v_bfe_u32 v6, v2, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 |
| ; VI-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 |
| ; VI-NEXT: v_alignbit_b32 v2, v2, v5, 16 |
| ; VI-NEXT: v_alignbit_b32 v1, v1, v4, 16 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16 |
| ; VI-NEXT: .LBB24_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6bf16_to_v6f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB24_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX9-NEXT: v_add3_u32 v5, v5, v4, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc |
| ; GFX9-NEXT: v_bfe_u32 v5, v1, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v5, v5, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc |
| ; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GFX9-NEXT: v_bfe_u32 v6, v5, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GFX9-NEXT: v_add3_u32 v6, v6, v5, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v7, 0x400000, v5 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc |
| ; GFX9-NEXT: v_bfe_u32 v6, v2, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v6, v6, v2, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v2, v5, v2, s6 |
| ; GFX9-NEXT: v_perm_b32 v1, v4, v1, s6 |
| ; GFX9-NEXT: v_perm_b32 v0, v3, v0, s6 |
| ; GFX9-NEXT: .LBB24_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6bf16_to_v6f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB24_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GFX11-NEXT: v_bfe_u32 v11, v5, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v5 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add3_u32 v11, v11, v5, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_bfe_u32 v8, v4, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v8, v8, v4, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0 |
| ; GFX11-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1 |
| ; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v3 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 |
| ; GFX11-NEXT: v_bfe_u32 v7, v0, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff |
| ; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_add3_u32 v7, v7, v0, 0x7fff |
| ; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo |
| ; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; GFX11-NEXT: v_bfe_u32 v9, v1, 16, 1 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc_lo |
| ; GFX11-NEXT: v_add3_u32 v8, v9, v1, 0x7fff |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: v_bfe_u32 v6, v2, 16, 1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v2, 0x7fff |
| ; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v13, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: v_perm_b32 v2, v5, v2, 0x7060302 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v10, vcc_lo |
| ; GFX11-NEXT: v_perm_b32 v1, v4, v1, 0x7060302 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_perm_b32 v0, v3, v0, 0x7060302 |
| ; GFX11-NEXT: .LBB24_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <6 x bfloat> %a1 to <6 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x bfloat> %a to <6 x half> |
| br label %end |
| |
| end: |
| %phi = phi <6 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x half> %phi |
| } |
| |
| define <6 x bfloat> @bitcast_v6f16_to_v6bf16(<6 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f16_to_v6bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB25_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB25_4 |
| ; GCN-NEXT: .LBB25_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB25_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB25_2 |
| ; GCN-NEXT: .LBB25_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v6 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f16_to_v6bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB25_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v4, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v1, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v6, 0x200, v2 |
| ; VI-NEXT: v_add_f16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v6, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, v5, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v3, v0 |
| ; VI-NEXT: .LBB25_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f16_to_v6bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f16_to_v6bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <6 x half> %a1 to <6 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x half> %a to <6 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <6 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x bfloat> %phi |
| } |
| |
| define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6bf16_to_v6i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v4 |
| ; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB26_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB26_4 |
| ; GCN-NEXT: .LBB26_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB26_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v8 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB26_2 |
| ; GCN-NEXT: .LBB26_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v11 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v10 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v8 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v7 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x40c00000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x40c00000, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v4 |
| ; GCN-NEXT: v_alignbit_b32 v0, v7, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v4, v5, v2, 16 |
| ; GCN-NEXT: v_alignbit_b32 v2, v3, v6, 16 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6bf16_to_v6i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB26_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; VI-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4 |
| ; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v1 |
| ; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5 |
| ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc |
| ; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5 |
| ; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc |
| ; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v2 |
| ; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; VI-NEXT: v_bfe_u32 v6, v5, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6 |
| ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 |
| ; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 |
| ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc |
| ; VI-NEXT: v_bfe_u32 v6, v2, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 |
| ; VI-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 |
| ; VI-NEXT: v_alignbit_b32 v2, v2, v5, 16 |
| ; VI-NEXT: v_alignbit_b32 v1, v1, v4, 16 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16 |
| ; VI-NEXT: .LBB26_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6bf16_to_v6i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB26_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 |
| ; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v3, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc |
| ; GFX9-NEXT: v_bfe_u32 v4, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v4, v4, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc |
| ; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX9-NEXT: v_add3_u32 v5, v5, v4, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc |
| ; GFX9-NEXT: v_bfe_u32 v5, v1, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v5, v5, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc |
| ; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GFX9-NEXT: v_bfe_u32 v6, v5, 16, 1 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GFX9-NEXT: v_add3_u32 v6, v6, v5, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v7, 0x400000, v5 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc |
| ; GFX9-NEXT: v_bfe_u32 v6, v2, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v6, v6, v2, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v2, v5, v2, s6 |
| ; GFX9-NEXT: v_perm_b32 v1, v4, v1, s6 |
| ; GFX9-NEXT: v_perm_b32 v0, v3, v0, s6 |
| ; GFX9-NEXT: .LBB26_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6bf16_to_v6i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB26_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 |
| ; GFX11-NEXT: v_bfe_u32 v11, v5, 16, 1 |
| ; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v5 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add3_u32 v11, v11, v5, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_bfe_u32 v8, v4, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v8, v8, v4, 0x7fff |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0 |
| ; GFX11-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1 |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1 |
| ; GFX11-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v3 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 |
| ; GFX11-NEXT: v_bfe_u32 v7, v0, 16, 1 |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff |
| ; GFX11-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_add3_u32 v7, v7, v0, 0x7fff |
| ; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo |
| ; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v4 |
| ; GFX11-NEXT: v_bfe_u32 v9, v1, 16, 1 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 |
| ; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc_lo |
| ; GFX11-NEXT: v_add3_u32 v8, v9, v1, 0x7fff |
| ; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: v_bfe_u32 v6, v2, 16, 1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 |
| ; GFX11-NEXT: v_add3_u32 v6, v6, v2, 0x7fff |
| ; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v13, vcc_lo |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: v_perm_b32 v2, v5, v2, 0x7060302 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v10, vcc_lo |
| ; GFX11-NEXT: v_perm_b32 v1, v4, v1, 0x7060302 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_perm_b32 v0, v3, v0, 0x7060302 |
| ; GFX11-NEXT: .LBB26_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <6 x bfloat> %a1 to <6 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x bfloat> %a to <6 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i16> %phi |
| } |
| |
| define <6 x bfloat> @bitcast_v6i16_to_v6bf16(<6 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i16_to_v6bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v9, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB27_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB27_4 |
| ; GCN-NEXT: .LBB27_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB27_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v9 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB27_2 |
| ; GCN-NEXT: .LBB27_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v9 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v5, v0 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v4 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v1 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i16_to_v6bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB27_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 3 |
| ; VI-NEXT: v_add_u16_sdwa v4, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v5, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v3, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v1 |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v5 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; VI-NEXT: .LBB27_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i16_to_v6bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i16_to_v6bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i16> %a, splat (i16 3) |
| %a2 = bitcast <6 x i16> %a1 to <6 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i16> %a to <6 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <6 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x bfloat> %phi |
| } |
| |
| define <6 x i16> @bitcast_v6f16_to_v6i16(<6 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f16_to_v6i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB28_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v3 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v6 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v7 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 |
| ; GCN-NEXT: .LBB28_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f16_to_v6i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB28_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v4, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v1, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v6, 0x200, v2 |
| ; VI-NEXT: v_add_f16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v6, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, v5, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v3, v0 |
| ; VI-NEXT: .LBB28_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f16_to_v6i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f16_to_v6i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <6 x half> %a1 to <6 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x half> %a to <6 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i16> %phi |
| } |
| |
| define <6 x half> @bitcast_v6i16_to_v6f16(<6 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i16_to_v6f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v12, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v9, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB29_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB29_4 |
| ; GCN-NEXT: .LBB29_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB29_3: ; %cmp.false |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB29_2 |
| ; GCN-NEXT: .LBB29_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v9 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v10 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i16_to_v6f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB29_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 3 |
| ; VI-NEXT: v_add_u16_sdwa v4, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v5, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v3, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v1 |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v5 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; VI-NEXT: .LBB29_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i16_to_v6f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i16_to_v6f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i16> %a, splat (i16 3) |
| %a2 = bitcast <6 x i16> %a1 to <6 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i16> %a to <6 x half> |
| br label %end |
| |
| end: |
| %phi = phi <6 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x half> %phi |
| } |
