; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib %s | FileCheck %s

define float @test_tdo_scalar_f32_asinpi() {
; CHECK-LABEL: define float @test_tdo_scalar_f32_asinpi() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float 0.000000e+00
;
entry:
  %c = call float @_Z6asinpif(float 0.000000e+00)
  ret float %c
}

define <4 x float> @test_tdo_v2_f32_asinpi() {
; CHECK-LABEL: define <4 x float> @test_tdo_v2_f32_asinpi() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float 5.000000e-01, float -5.000000e-01>
;
entry:
  %c = call <4 x float> @_Z6asinpiDv4_f(<4 x float> <float 0.000000e+00, float -0.000000e+00, float 1.000000e+00, float -1.000000e+00>)
  ret <4 x float> %c
}

define half @test_tdo_scalar_f16_asinpi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_asinpi() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret half 0xH0000
;
entry:
  %c = call half @_Z6asinpiDh(half 0.000000e+00)
  ret half %c
}

define <4 x half> @test_tdo_v2_f16_asinpi() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_asinpi() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3800, half 0xHB800>
;
entry:
  %c = call <4 x half> @_Z6asinpiDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
  ret <4 x half> %c
}

define double @test_tdo_scalar_f64_asinpi() {
; CHECK-LABEL: define double @test_tdo_scalar_f64_asinpi() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret double 0.000000e+00
;
entry:
  %c = call double @_Z6asinpid(double 0.000000e+00)
  ret double %c
}

define <4 x double> @test_tdo_v2_f64_asinpi() {
; CHECK-LABEL: define <4 x double> @test_tdo_v2_f64_asinpi() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret <4 x double> <double 0.000000e+00, double -0.000000e+00, double 5.000000e-01, double -5.000000e-01>
;
entry:
  %c = call <4 x double> @_Z6asinpiDv4_d(<4 x double> <double 0.000000e+00, double -0.000000e+00, double 1.000000e+00, double -1.000000e+00>)
  ret <4 x double> %c
}

declare float        @_Z6asinpif(float)
declare <4 x float>  @_Z6asinpiDv4_f(<4 x float>)
declare half         @_Z6asinpiDh(half)
declare <4 x half>   @_Z6asinpiDv4_Dh(<4 x half>)
declare double       @_Z6asinpid(double)
declare <4 x double> @_Z6asinpiDv4_d(<4 x double>)