[RISCV] Add th.ext(u) to RISCVDAGToDAGISel::hasAllNBitUsers. (#157133)
These instructions are being used by the scalar efficiency SIG to
determine if we should have a standard instruction. Improving our
support for these instructions may give better data for their analysis.
I'll follow up by adding this to RISCVOptWInstrs too which will remove
the 'w' suffixes added here.
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 142414d..e84bf0e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3937,6 +3937,15 @@
if (Use.getOperandNo() == 0 && Bits >= 32)
break;
return false;
+ case RISCV::TH_EXT:
+ case RISCV::TH_EXTU: {
+ unsigned Msb = User->getConstantOperandVal(1);
+ unsigned Lsb = User->getConstantOperandVal(2);
+ // Behavior of Msb < Lsb is not well documented.
+ if (Msb >= Lsb && Bits > Msb)
+ break;
+ return false;
+ }
}
}
diff --git a/llvm/test/CodeGen/RISCV/bitextract-mac.ll b/llvm/test/CodeGen/RISCV/bitextract-mac.ll
index 41a3265..71066b2 100644
--- a/llvm/test/CodeGen/RISCV/bitextract-mac.ll
+++ b/llvm/test/CodeGen/RISCV/bitextract-mac.ll
@@ -107,7 +107,7 @@
;
; RV64XTHEADBB-LABEL: f:
; RV64XTHEADBB: # %bb.0: # %entry
-; RV64XTHEADBB-NEXT: mul a0, a1, a0
+; RV64XTHEADBB-NEXT: mulw a0, a1, a0
; RV64XTHEADBB-NEXT: th.extu a1, a0, 5, 2
; RV64XTHEADBB-NEXT: th.extu a0, a0, 11, 5
; RV64XTHEADBB-NEXT: mul a0, a1, a0
@@ -116,7 +116,7 @@
;
; RV64XTHEAD-LABEL: f:
; RV64XTHEAD: # %bb.0: # %entry
-; RV64XTHEAD-NEXT: mul a0, a1, a0
+; RV64XTHEAD-NEXT: mulw a0, a1, a0
; RV64XTHEAD-NEXT: th.extu a1, a0, 5, 2
; RV64XTHEAD-NEXT: th.extu a0, a0, 11, 5
; RV64XTHEAD-NEXT: th.mulah a2, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 908a123..c253382 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -2438,7 +2438,7 @@
; RV64XTHEADBB-NEXT: and a0, a0, a2
; RV64XTHEADBB-NEXT: add a0, a1, a0
; RV64XTHEADBB-NEXT: srli a1, a0, 4
-; RV64XTHEADBB-NEXT: add a0, a0, a1
+; RV64XTHEADBB-NEXT: addw a0, a0, a1
; RV64XTHEADBB-NEXT: th.extu a1, a0, 11, 8
; RV64XTHEADBB-NEXT: andi a0, a0, 15
; RV64XTHEADBB-NEXT: add a0, a0, a1
