# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            zextload_s32_from_s16
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s16
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
    %0:gpr(p0) = COPY $x0
    %1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16))
    $w0 = COPY %1(s32)
...
---
name:            zextload_s32_from_s16_not_combined
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
    ; CHECK-NEXT: $w0 = COPY [[COPY1]]
    %0:gpr(p0) = COPY $x0
    %1:gpr(s16) = G_LOAD %0 :: (load (s16))
    %2:gpr(s32) = G_ZEXT %1
    $w0 = COPY %2(s32)
...
---
name:            i32_to_i64
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: i32_to_i64
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32
    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...
---
name:            i16_to_i64
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: i16_to_i64
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32
    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...
---
name:            i8_to_i64
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: i8_to_i64
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...
---
name:            i8_to_i32
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: i8_to_i32
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
    ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            i16_to_i32
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: i16_to_i32
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s8_atomic_unordered
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_unordered
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load unordered (s8))
    ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s8_atomic_monotonic
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_monotonic
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load monotonic (s8))
    ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s8_atomic_acquire
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_acquire
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (s8))
    ; CHECK-NEXT: $w0 = COPY [[LDARB]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s8_atomic_seq_cst
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_seq_cst
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst (s8))
    ; CHECK-NEXT: $w0 = COPY [[LDARB]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s16_atomic_unordered
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_unordered
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load unordered (s16))
    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s16_atomic_monotonic
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_monotonic
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load monotonic (s16))
    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s16_atomic_acquire
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_acquire
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load acquire (s16))
    ; CHECK-NEXT: $w0 = COPY [[LDARH]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...

---
name: zextload_s32_from_s16_atomic_seq_cst
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_seq_cst
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load seq_cst (s16))
    ; CHECK-NEXT: $w0 = COPY [[LDARH]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(p0) = COPY $x0
    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))
    $w0 = COPY %2
    RET_ReallyLR implicit $w0

...