tree 2ca001a2f27fb17147c560be8c1a4962327833fb
parent ba87430cadb2d5d0ee8e4b75101d7abcf6b321bf
author Scott Constable <scott.d.constable@intel.com> 1585936718 -0700
committer Craig Topper <craig.topper@intel.com> 1585940914 -0700

[X86] Add RET-hardening Support to mitigate Load Value Injection (LVI)

Adding a pass that replaces every ret instruction with the sequence:

pop <scratch-reg>
lfence
jmp *<scratch-reg>

where <scratch-reg> is some available scratch register, according to the
calling convention of the function being mitigated.

Differential Revision: https://reviews.llvm.org/D75935