MachineIRBuilder: Rename buildMerge. NFC
`buildMerge` may build a G_MERGE_VALUES, G_BUILD_VECTOR or
G_CONCAT_VECTORS. Rename it to `buildMergeLikeInstr`.
This is a follow-up suggested in https://reviews.llvm.org/D140964
Differential Revision: https://reviews.llvm.org/D141372
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index e21de08..8a1fce2 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -235,7 +235,7 @@
// Requested sub-vectors of NarrowTy.
for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) {
ArrayRef<Register> Pieces(&Elts[Offset], NumElts);
- VRegs.push_back(MIRBuilder.buildMerge(NarrowTy, Pieces).getReg(0));
+ VRegs.push_back(MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0));
}
// Leftover element(s).
@@ -244,7 +244,8 @@
} else {
LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy);
ArrayRef<Register> Pieces(&Elts[Offset], LeftoverNumElts);
- VRegs.push_back(MIRBuilder.buildMerge(LeftoverTy, Pieces).getReg(0));
+ VRegs.push_back(
+ MIRBuilder.buildMergeLikeInstr(LeftoverTy, Pieces).getReg(0));
}
}
@@ -257,7 +258,7 @@
assert(LeftoverRegs.empty());
if (!ResultTy.isVector()) {
- MIRBuilder.buildMerge(DstReg, PartRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, PartRegs);
return;
}
@@ -306,7 +307,7 @@
else
appendVectorElts(AllElts, Leftover);
- MIRBuilder.buildMerge(DstReg, AllElts);
+ MIRBuilder.buildMergeLikeInstr(DstReg, AllElts);
}
/// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs.
@@ -423,7 +424,7 @@
if (NumSubParts == 1)
Remerge[I] = SubMerge[0];
else
- Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0);
+ Remerge[I] = MIRBuilder.buildMergeLikeInstr(NarrowTy, SubMerge).getReg(0);
// In the sign extend padding case, re-use the first all-signbit merge.
if (AllMergePartsArePadding && !AllPadReg)
@@ -442,11 +443,11 @@
// the result.
if (DstTy == LCMTy) {
- MIRBuilder.buildMerge(DstReg, RemergeRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, RemergeRegs);
return;
}
- auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs);
+ auto Remerge = MIRBuilder.buildMergeLikeInstr(LCMTy, RemergeRegs);
if (DstTy.isScalar() && LCMTy.isScalar()) {
MIRBuilder.buildTrunc(DstReg, Remerge);
return;
@@ -460,7 +461,7 @@
UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy);
MIRBuilder.buildUnmerge(UnmergeDefs,
- MIRBuilder.buildMerge(LCMTy, RemergeRegs));
+ MIRBuilder.buildMergeLikeInstr(LCMTy, RemergeRegs));
return;
}
@@ -941,7 +942,7 @@
if (DstTy.isVector())
MIRBuilder.buildBuildVector(DstReg, DstRegs);
else
- MIRBuilder.buildMerge(DstReg, DstRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, DstRegs);
MI.eraseFromParent();
return Legalized;
}
@@ -1013,7 +1014,7 @@
MIRBuilder.buildFreeze(NarrowTy, Unmerge.getReg(i)).getReg(0));
}
- MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Parts);
+ MIRBuilder.buildMergeLikeInstr(MI.getOperand(0).getReg(), Parts);
MI.eraseFromParent();
return Legalized;
}
@@ -1188,7 +1189,7 @@
MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
}
MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
- MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
+ MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), DstRegs);
Observer.changedInstr(MI);
MI.eraseFromParent();
return Legalized;
@@ -1365,7 +1366,7 @@
// Gather the destination registers into the final destination.
Register DstReg = MI.getOperand(0).getReg();
- MIRBuilder.buildMerge(DstReg, DstRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, DstRegs);
MI.eraseFromParent();
return Legalized;
}
@@ -1385,7 +1386,7 @@
DstRegs.push_back(DstPart.getReg(0));
}
- MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
+ MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), DstRegs);
Observer.changedInstr(MI);
MI.eraseFromParent();
@@ -1602,16 +1603,17 @@
// Build merges of each piece.
ArrayRef<Register> Slicer(Unmerges);
for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
- auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
+ auto Merge =
+ MIRBuilder.buildMergeLikeInstr(WideTy, Slicer.take_front(PartsPerGCD));
NewMergeRegs.push_back(Merge.getReg(0));
}
// A truncate may be necessary if the requested type doesn't evenly divide the
// original result type.
if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
- MIRBuilder.buildMerge(DstReg, NewMergeRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, NewMergeRegs);
} else {
- auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
+ auto FinalMerge = MIRBuilder.buildMergeLikeInstr(WideDstTy, NewMergeRegs);
MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
}
@@ -1739,7 +1741,7 @@
RemergeParts.emplace_back(Parts[Idx]);
}
- MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts);
+ MIRBuilder.buildMergeLikeInstr(MI.getOperand(I).getReg(), RemergeParts);
RemergeParts.clear();
}
}
@@ -2680,7 +2682,7 @@
} else
getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy);
- MIRBuilder.buildMerge(Dst, SrcRegs);
+ MIRBuilder.buildMergeLikeInstr(Dst, SrcRegs);
MI.eraseFromParent();
return Legalized;
}
@@ -2688,7 +2690,7 @@
if (DstTy.isVector()) {
SmallVector<Register, 8> SrcRegs;
getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
- MIRBuilder.buildMerge(Dst, SrcRegs);
+ MIRBuilder.buildMergeLikeInstr(Dst, SrcRegs);
MI.eraseFromParent();
return Legalized;
}
@@ -3760,7 +3762,7 @@
mergeMixedSubvectors(MI.getReg(i), OutputRegs[i]);
} else {
for (unsigned i = 0; i < NumDefs; ++i)
- MIRBuilder.buildMerge(MI.getReg(i), OutputRegs[i]);
+ MIRBuilder.buildMergeLikeInstr(MI.getReg(i), OutputRegs[i]);
}
MI.eraseFromParent();
@@ -3808,7 +3810,7 @@
if (NumLeftovers) {
mergeMixedSubvectors(MI.getReg(0), OutputRegs);
} else {
- MIRBuilder.buildMerge(MI.getReg(0), OutputRegs);
+ MIRBuilder.buildMergeLikeInstr(MI.getReg(0), OutputRegs);
}
MI.eraseFromParent();
@@ -3911,10 +3913,11 @@
for (unsigned i = 0, Offset = 0; i < NumNarrowTyPieces;
++i, Offset += NumNarrowTyElts) {
ArrayRef<Register> Pieces(&Elts[Offset], NumNarrowTyElts);
- NarrowTyElts.push_back(MIRBuilder.buildMerge(NarrowTy, Pieces).getReg(0));
+ NarrowTyElts.push_back(
+ MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0));
}
- MIRBuilder.buildMerge(DstReg, NarrowTyElts);
+ MIRBuilder.buildMergeLikeInstr(DstReg, NarrowTyElts);
MI.eraseFromParent();
return Legalized;
}
@@ -3942,10 +3945,11 @@
SmallVector<Register, 8> Sources;
for (unsigned j = 0; j < NumElts; ++j)
Sources.push_back(MI.getOperand(1 + i * NumElts + j).getReg());
- NarrowTyElts.push_back(MIRBuilder.buildMerge(NarrowTy, Sources).getReg(0));
+ NarrowTyElts.push_back(
+ MIRBuilder.buildMergeLikeInstr(NarrowTy, Sources).getReg(0));
}
- MIRBuilder.buildMerge(DstReg, NarrowTyElts);
+ MIRBuilder.buildMergeLikeInstr(DstReg, NarrowTyElts);
MI.eraseFromParent();
return Legalized;
}
@@ -4588,7 +4592,7 @@
MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
if (Amt.isZero()) {
- MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
+ MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), {InL, InH});
MI.eraseFromParent();
return Legalized;
}
@@ -4661,7 +4665,7 @@
}
}
- MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi});
+ MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), {Lo, Hi});
MI.eraseFromParent();
return Legalized;
@@ -4772,7 +4776,7 @@
llvm_unreachable("not a shift");
}
- MIRBuilder.buildMerge(DstReg, ResultRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, ResultRegs);
MI.eraseFromParent();
return Legalized;
}
@@ -5239,7 +5243,7 @@
// Take only high half of registers if this is high mul.
ArrayRef<Register> DstRegs(&DstTmpRegs[DstTmpParts - NumParts], NumParts);
- MIRBuilder.buildMerge(DstReg, DstRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, DstRegs);
MI.eraseFromParent();
return Legalized;
}
@@ -5329,7 +5333,7 @@
if (MRI.getType(DstReg).isVector())
MIRBuilder.buildBuildVector(DstReg, DstRegs);
else if (DstRegs.size() > 1)
- MIRBuilder.buildMerge(DstReg, DstRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, DstRegs);
else
MIRBuilder.buildCopy(DstReg, DstRegs[0]);
MI.eraseFromParent();
@@ -5411,10 +5415,10 @@
Register DstReg = MI.getOperand(0).getReg();
if (WideSize > RegTy.getSizeInBits()) {
Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize));
- MIRBuilder.buildMerge(MergeReg, DstRegs);
+ MIRBuilder.buildMergeLikeInstr(MergeReg, DstRegs);
MIRBuilder.buildTrunc(DstReg, MergeReg);
} else
- MIRBuilder.buildMerge(DstReg, DstRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, DstRegs);
MI.eraseFromParent();
return Legalized;
@@ -6672,7 +6676,7 @@
if (InsertVal) {
SrcRegs[IdxVal] = MI.getOperand(2).getReg();
- MIRBuilder.buildMerge(DstReg, SrcRegs);
+ MIRBuilder.buildMergeLikeInstr(DstReg, SrcRegs);
} else {
MIRBuilder.buildCopy(DstReg, SrcRegs[IdxVal]);
}
@@ -6844,7 +6848,7 @@
if (SubVectorElts.size() == 1)
MIRBuilder.buildCopy(Dst, SubVectorElts[0]);
else
- MIRBuilder.buildMerge(Dst, SubVectorElts);
+ MIRBuilder.buildMergeLikeInstr(Dst, SubVectorElts);
MI.eraseFromParent();
return Legalized;
@@ -6917,7 +6921,7 @@
DstElts.push_back(UnmergeSrc.getReg(Idx));
}
- MIRBuilder.buildMerge(Dst, DstElts);
+ MIRBuilder.buildMergeLikeInstr(Dst, DstElts);
MI.eraseFromParent();
return Legalized;
}
