)]}'
{
  "commit": "f3f717bbfa61600703b3b2149ebdb87fbee2dbac",
  "tree": "ee20af3505cd4f354eba9df5a3ed47f9e2818c02",
  "parents": [
    "31c9198ea0f9651b8d18548d4a4bff252680f804"
  ],
  "author": {
    "name": "Craig Topper",
    "email": "craig.topper@sifive.com",
    "time": "Sat Aug 30 18:27:18 2025 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Sat Aug 30 18:27:18 2025 -0700"
  },
  "message": "[RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)\n\nThis node reads the lower 32 bits, shifts it right arithmetically\nthen sign extends to i64. If we know some of the lower 32 bits we\ncan propagate that information.\n    \nFor the test case I had to find something that didn\u0027t get optimized\nbefore type legalizaton and didn\u0027t get type legalized to a sign\nextended value. The bswap gets type legalized to (lshr (bswap), 32).",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9c268012b24d2ef77d797b24bc1718f89e35aa05",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVISelLowering.cpp",
      "new_id": "9115c1385d6df59271c707a43b09a1f94732b097",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVISelLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "90735d88494b5186182e3bdd5da88b98d2b5515f",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll",
      "new_id": "b23f4f5812000f927586eceddab90da6337383af",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll"
    }
  ]
}