tree c2d734193f5534e31d734b706254e382eb26dedd
parent 3de89abf189e63da4edbfda509ed3d421bdba1a9
author David Green <david.green@arm.com> 1587934738 +0100
committer Tom Stellard <tstellar@redhat.com> 1589915466 -0700

[ARM] Only produce qadd8b under hasV6Ops

When compiling for a arm5te cpu from clang, the +dsp attribute is set.
This meant we could try and generate qadd8 instructions where we would
end up having no pattern. I've changed the condition here to be hasV6Ops
&& hasDSP, which is what other parts of ARMISelLowering seem to use for
similar instructions.

Fixed PR45677.

Differential Revision: https://reviews.llvm.org/D78877

(cherry picked from commit 8807139026b64ac40163bb255dad38a1d8054f08)