[RISCV] Fix RISCVInsertVSETVLI coalescing clobbering VL def segment (#167712)

This fixes an assert when compiling llvm-test-suite with -march=rva23u64
-O3 that started appearing sometime this week.

We get "Cannot overlap two segments with differing ValID's" because we
try to coalescse these two vsetvlis:

    %x:gprnox0 = COPY $x8
dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
    %y:gprnox0 = COPY %x
    %v:vr = COPY $v8, implicit $vtype
    %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype

    -->

    %x:gprnox0 = COPY $x8
    %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
    %y:gprnox0 = COPY %x
    %v:vr = COPY $v8, implicit $vtype

However to do so would cause us to extend the segment of the new value
of %x up past the first segment, which overlaps.

This fixes it by checking that its safe to extend the segment, by simply
making sure the interval isn't live at the first vsetvli.

This unfortunately causes a regression in the existing
coalesce_vl_avl_same_reg test because even though we could coalesce the
vsetvlis there, we now bail. I couldn't think of an easy way to handle
this safely, but I don't think this is an important case to handle:
After testing this patch on SPEC CPU 2017 there are no codegen changes.