)]}'
{
  "commit": "f261f1406d4870410d3c9e61903e65ffd427d8ec",
  "tree": "5adf278490ef58842fed795c66f806c74c7e3829",
  "parents": [
    "c8dc3ed9c464580273c2d91b8ec769d4f0193a1b"
  ],
  "author": {
    "name": "Craig Topper",
    "email": "craig.topper@sifive.com",
    "time": "Thu Apr 24 12:14:05 2025 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Apr 24 12:14:05 2025 -0700"
  },
  "message": "[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic_load. (#137119)\n\nAnd teach SelectionDAGBuilder to get the range metadata in\nvisitAtomicLoad.\n\nThis allows us to recognize that sign extending a byte load of a\nboolean value from memory will produce zeros for the extended bits.\nThis allow us to remove an AND on RISC-V.\n\nTests copied from #136502 with range metadata added to i1 cases.\nSome of the test effects overlap with #136502, but that patch can\u0027t\nhandle the acquire or seq_cst cases with the Zalasr extension. We\nonly have sign extending versions of those loads.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cf88c1f4ae937ea5006d6829bc2fa9749066ed64",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp",
      "new_id": "3b2dafc9e0fa89d195402f0d07a058841a1796b7",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp"
    },
    {
      "type": "modify",
      "old_id": "66bd78af2939c78c9beb53243894fc842042bdb1",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp",
      "new_id": "4b05d89417d2c589a950c90839554cdc8e1e6ccf",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "80971794437918b8d0650f9a9199ff32702c8e7e",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/RISCV/atomic-load-zext.ll"
    }
  ]
}