tree 8949c2a9e112a7705aa2f7b21a0e2e19109a1fd4
parent e8cded57fbf7b2b81aefd569b95f38ae97948ef0
author Craig Topper <craig.topper@sifive.com> 1624575227 -0700
committer Craig Topper <craig.topper@sifive.com> 1624583196 -0700

[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D104822