)]}'
{
  "commit": "f134b802ee5ec127f178dd0c93de40f7e83a1c27",
  "tree": "a13c65e7009520cd0f0641f94abdd622a3536a93",
  "parents": [
    "f668c9ff2b2775fa749b92985ad65f3f0f2132ed"
  ],
  "author": {
    "name": "Craig Topper",
    "email": "craig.topper@sifive.com",
    "time": "Tue Feb 10 12:34:15 2026 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Feb 10 12:34:15 2026 -0800"
  },
  "message": "[RISCV] Refactor the MC layer SiFive VCIX classes. (#180433)\n\nMy initial goal was to name bits {19-15} as either rs1, vs1, or imm as\nappropriate.\n\nThe VCIX instructions effectively have 3 properties that are combined:\nthe type of bits 19-15 (determined by funct3), how many vector registers\nare sources (determined by funct6), and whether vd is a written or not\n(determined by vm).\n\nI found the VCIXInfo class very hard to read and understand. This patch\nbreaks it up into simpler steps and moves some properties to flags in\nthe existing VCIXType classs. A new VCIXRs1Info class is added to\ncontain the properties for bits 19-15. The VCIXInfo now combines the\nproperties from these 2 classes and the HaveOutputDst flag to create the\nvarious things needed to build the final instruction. To reduce the\nnumber of template arguments, the VCIXInfo is passed all the way down to\nthe base class.\n\nMuch of the refactoring in this patch was accomplished with AI. I have\nlooked at the diffs in the output tablegen files to verify it works as\nexpected. RISCVGenInstrInfo.inc only changes line number comments.\nRISCVGenDisassembler.inc doesn\u0027t change at all as expected.\nRISCVGenMCCodeEmitter.inc changes due to the different field names and\norders in the record.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6051cf1aa5abf1263d12deb287eb743f4875c0f0",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td",
      "new_id": "bc65db1f77ffbe380dd9cddc2724b005ecec788d",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td"
    }
  ]
}