[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
We have lots of uses of `report_fatal_error` in the backend, which will
result in a crash and a backtrace. This API has been replaced with
`reportFatalUsageError` and `reportFatalInternalError`, for which only
the latter emits a stack trace.
This tries to move the errors in RISCVISelLowering and RISCVRegisterInfo
to the new APIs, to prevent some stack traces where we specificially do
not support certain situations.
Updates #124132
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7d4dd14..a332248 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -109,7 +109,7 @@
switch (ABI) {
default:
- report_fatal_error("Don't know how to lower this ABI");
+ reportFatalUsageError("Don't know how to lower this ABI");
case RISCVABI::ABI_ILP32:
case RISCVABI::ABI_ILP32E:
case RISCVABI::ABI_LP64E:
@@ -7305,7 +7305,8 @@
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
- report_fatal_error("unimplemented operand");
+ reportFatalInternalError(
+ "Unimplemented RISCVTargetLowering::LowerOperation Case");
case ISD::PREFETCH:
return LowerPREFETCH(Op, Subtarget, DAG);
case ISD::ATOMIC_FENCE:
@@ -7503,7 +7504,7 @@
// vscale as VLENB / 8.
static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
- report_fatal_error("Support for VLEN==32 is incomplete.");
+ reportFatalInternalError("Support for VLEN==32 is incomplete.");
// We assume VLENB is a multiple of 8. We manually choose the best shift
// here because SimplifyDemandedBits isn't always able to simplify it.
uint64_t Val = Op.getConstantOperandVal(0);
@@ -8516,7 +8517,7 @@
SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
SelectionDAG &DAG) const {
if (!Subtarget.is64Bit())
- llvm::report_fatal_error("Trampolines only implemented for RV64");
+ llvm::reportFatalUsageError("Trampolines only implemented for RV64");
// Create an MCCodeEmitter to encode instructions.
TargetLoweringObjectFile *TLO = getTargetMachine().getObjFileLowering();
@@ -8676,7 +8677,7 @@
SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
SelectionDAG &DAG) const {
if (!Subtarget.is64Bit())
- llvm::report_fatal_error("Trampolines only implemented for RV64");
+ llvm::reportFatalUsageError("Trampolines only implemented for RV64");
return Op.getOperand(0);
}
@@ -8811,7 +8812,7 @@
switch (getTargetMachine().getCodeModel()) {
default:
- report_fatal_error("Unsupported code model for lowering");
+ reportFatalUsageError("Unsupported code model for lowering");
case CodeModel::Small: {
// Generate a sequence for accessing addresses within the first 2 GiB of
// address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
@@ -8989,7 +8990,7 @@
if (DAG.getMachineFunction().getFunction().getCallingConv() ==
CallingConv::GHC)
- report_fatal_error("In GHC calling convention TLS is not supported");
+ reportFatalUsageError("In GHC calling convention TLS is not supported");
SDValue Addr;
switch (Model) {
@@ -10838,7 +10839,7 @@
if (!isValidEGW(4, Op.getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(1).getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(2).getSimpleValueType(), Subtarget))
- report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
+ reportFatalUsageError("EGW should be greater than or equal to 4 * SEW.");
return Op;
}
// EGS * EEW >= 256 bits
@@ -10846,7 +10847,7 @@
case Intrinsic::riscv_vsm3me: {
if (!isValidEGW(8, Op.getSimpleValueType(), Subtarget) ||
!isValidEGW(8, Op->getOperand(1).getSimpleValueType(), Subtarget))
- report_fatal_error("EGW should be greater than or equal to 8 * SEW.");
+ reportFatalUsageError("EGW should be greater than or equal to 8 * SEW.");
return Op;
}
// zvknha(SEW=32)/zvknhb(SEW=[32|64])
@@ -10855,11 +10856,11 @@
case Intrinsic::riscv_vsha2ms: {
if (Op->getSimpleValueType(0).getScalarSizeInBits() == 64 &&
!Subtarget.hasStdExtZvknhb())
- report_fatal_error("SEW=64 needs Zvknhb to be enabled.");
+ reportFatalUsageError("SEW=64 needs Zvknhb to be enabled.");
if (!isValidEGW(4, Op.getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(1).getSimpleValueType(), Subtarget) ||
!isValidEGW(4, Op->getOperand(2).getSimpleValueType(), Subtarget))
- report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
+ reportFatalUsageError("EGW should be greater than or equal to 4 * SEW.");
return Op;
}
case Intrinsic::riscv_sf_vc_v_x:
@@ -22334,8 +22335,8 @@
case TargetOpcode::STACKMAP:
case TargetOpcode::PATCHPOINT:
if (!Subtarget.is64Bit())
- report_fatal_error("STACKMAP, PATCHPOINT and STATEPOINT are only "
- "supported on 64-bit targets");
+ reportFatalUsageError("STACKMAP, PATCHPOINT and STATEPOINT are only "
+ "supported on 64-bit targets");
return emitPatchPoint(MI, BB);
}
}
@@ -22568,7 +22569,7 @@
switch (CallConv) {
default:
- report_fatal_error("Unsupported calling convention");
+ reportFatalUsageError("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
case CallingConv::SPIR_KERNEL:
@@ -22592,17 +22593,17 @@
break;
case CallingConv::GHC:
if (Subtarget.hasStdExtE())
- report_fatal_error("GHC calling convention is not supported on RVE!");
+ reportFatalUsageError("GHC calling convention is not supported on RVE!");
if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
- report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
- "(Zdinx/D) instruction set extensions");
+ reportFatalUsageError("GHC calling convention requires the (Zfinx/F) and "
+ "(Zdinx/D) instruction set extensions");
}
const Function &Func = MF.getFunction();
if (Func.hasFnAttribute("interrupt")) {
if (!Func.arg_empty())
- report_fatal_error(
- "Functions with the interrupt attribute cannot have arguments!");
+ reportFatalUsageError(
+ "Functions with the interrupt attribute cannot have arguments!");
StringRef Kind =
MF.getFunction().getFnAttribute("interrupt").getValueAsString();
@@ -22618,11 +22619,12 @@
"SiFive-CLIC-preemptible-stack-swap",
};
if (!llvm::is_contained(SupportedInterruptKinds, Kind))
- report_fatal_error(
- "Function interrupt attribute argument not supported!");
+ reportFatalUsageError(
+ "Function interrupt attribute argument not supported!");
if (Kind.starts_with("qci-") && !Subtarget.hasVendorXqciint())
- report_fatal_error("'qci-*' interrupt kinds require Xqciint extension");
+ reportFatalUsageError(
+ "'qci-*' interrupt kinds require Xqciint extension");
if (Kind.starts_with("SiFive-CLIC-") && !Subtarget.hasVendorXSfmclic())
reportFatalUsageError(
@@ -22860,7 +22862,7 @@
if (CallConv == CallingConv::GHC) {
if (Subtarget.hasStdExtE())
- report_fatal_error("GHC calling convention is not supported on RVE!");
+ reportFatalUsageError("GHC calling convention is not supported on RVE!");
ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
} else
analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI,
@@ -22874,8 +22876,8 @@
if (IsTailCall)
++NumTailCalls;
else if (CLI.CB && CLI.CB->isMustTailCall())
- report_fatal_error("failed to perform tail call elimination on a call "
- "site marked musttail");
+ reportFatalInternalError("failed to perform tail call elimination on a "
+ "call site marked musttail");
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = ArgCCInfo.getStackSize();
@@ -23200,7 +23202,7 @@
nullptr, CC_RISCV);
if (CallConv == CallingConv::GHC && !RVLocs.empty())
- report_fatal_error("GHC functions return void only");
+ reportFatalUsageError("GHC functions return void only");
SDValue Glue;
SmallVector<SDValue, 4> RetOps(1, Chain);
@@ -23266,7 +23268,7 @@
const Function &Func = DAG.getMachineFunction().getFunction();
if (Func.hasFnAttribute("interrupt")) {
if (!Func.getReturnType()->isVoidTy())
- report_fatal_error(
+ reportFatalUsageError(
"Functions with the interrupt attribute must have void return type!");
MachineFunction &MF = DAG.getMachineFunction();
@@ -24533,8 +24535,8 @@
BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg))
- report_fatal_error(Twine("Trying to obtain non-reserved register \"" +
- StringRef(RegName) + "\"."));
+ reportFatalUsageError(Twine("Trying to obtain non-reserved register \"" +
+ StringRef(RegName) + "\"."));
return Reg;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 440f6cf..f3966a5 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -170,7 +170,7 @@
if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
if (Subtarget.hasStdExtE())
- report_fatal_error("Graal reserved registers do not exist in RVE");
+ reportFatalUsageError("Graal reserved registers do not exist in RVE");
markSuperRegs(Reserved, RISCV::X23_H);
markSuperRegs(Reserved, RISCV::X27_H);
}
@@ -216,7 +216,7 @@
const int64_t NumOfVReg = Offset.getScalable() / 8;
const int64_t FixedOffset = NumOfVReg * VLENB;
if (!isInt<32>(FixedOffset)) {
- report_fatal_error(
+ reportFatalUsageError(
"Frame size outside of the signed 32-bit range not supported");
}
Offset = StackOffset::getFixed(FixedOffset + Offset.getFixed());
@@ -511,7 +511,7 @@
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
if (!isInt<32>(Offset.getFixed())) {
- report_fatal_error(
+ reportFatalUsageError(
"Frame offsets outside of the signed 32-bit range not supported");
}
diff --git a/llvm/test/CodeGen/RISCV/get-register-reserve.ll b/llvm/test/CodeGen/RISCV/get-register-reserve.ll
index 87acd70..7549b4d 100644
--- a/llvm/test/CodeGen/RISCV/get-register-reserve.ll
+++ b/llvm/test/CodeGen/RISCV/get-register-reserve.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \
+; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \
; RUN: | FileCheck -check-prefix=NO-RESERVE-A1 %s
-; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \
+; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \
; RUN: | FileCheck -check-prefix=NO-RESERVE-FP %s
; RUN: llc < %s -mtriple=riscv32 -mattr +reserve-x8 -mattr +reserve-x11 \
; RUN: | FileCheck -check-prefix=RESERVE %s
diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll
index f15f565..edc65bf 100644
--- a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll
+++ b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!
diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll
index 2bcec15..bddca8a 100644
--- a/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll
+++ b/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Function interrupt attribute argument not supported!
diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll
index 30fd8fb..eec9625 100644
--- a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll
+++ b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
index dd5d48a..9674b78 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
+; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
-; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
+; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
index 697c582..b45a768b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
+; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
-; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
+; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
index e57baa5..ff51acc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknha,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
+; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
-; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
+; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
