[AArch64] SME definitions for C1-Nano scheduling model (#207174) Extend the C1-Nano scheduling model to add support for SME instructions. These instructions differ from legacy scheduling model instruction definitions in that they are sent to the CME co-processor when in streaming mode. Modelling these instructions requires several changes to the scheduling model - definitions of CME processor resources. Instructions sent to this co-processor are modelled as having latency derived from the SME software optimization guide (SWOG), - predicating the process resource groups for instructions sent to the CME co-processor when in streaming mode, tests for all SME instructions in the software optimization guide Currently the C1-Nano SWOG lacks details of the following, so are not currently implemented: - instructions added by SME but don't require the processor to be in streaming mode C1-Nano SWOG: https://developer.arm.com/documentation/109590/0001 SME SWOG: https://developer.arm.com/documentation/111048/0103 The changes are modelled on the addition to the C1-Ultra scheduling model to support SME.
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