| commit | 9de49703b82e8e3d45d2e1ceb2626f5bb920ee12 | [log] [tgz] |
|---|---|---|
| author | Farzon Lotfi <farzonlotfi@microsoft.com> | Wed Jul 30 14:38:33 2025 -0400 |
| committer | GitHub <noreply@github.com> | Wed Jul 30 14:38:33 2025 -0400 |
| tree | 9022eabb44ed5139ddc7e50ec3049895509d90f8 | |
| parent | 3b5aff569d0604d554a6648920cc627d71748ae4 [diff] |
[SPIRV] Preserve implicit bitcast (#151041) fixes #146942 ## Issue The cause of the bug is in InstCombine which is converting our load of float vec4 and bitcast to i32 vec4 into one load of i32 vec4. That means wr have to do a legalization in the spirv backend to convert back ```diff - %3 = load <4 x i32>, ptr addrspace(11) %2, align 16 + %3 = load <4 x float>, ptr addrspace(11) %2, align 16 + %4 = bitcast <4 x float> %3 to <4 x i32> ``` <img width="2566" height="548" alt="Image" src="https://github.com/user-attachments/assets/0bf8813c-70f8-47df-8207-ab7da54f5382" /> https://godbolt.org/z/K4GeM4fKT ## The Fix Just removing the assert isn't enough to fix this bug. If we do so we get an assert later `Assertion failed: (!storageClassRequiresExplictLayout(SC)), function getOrCreateSPIRVPointerType, file SPIRVGlobalRegistry.cpp, line 1806.` If we just remove the assert the `CreateShuffleVector` uses the source type via the `NewLoad` when the `Output` type needs to be the `TargetType`. We also can't use`CreateBitCast` That will feed the right types for the `ShuffleVector` but it doesn't emit OpBitcast. the llvmIR isn't translated over to MIR. The fix then is to emit `spv_bitcast` just like what `SPIRVEmitIntrinsics::visitBitCastInst` does. --------- Co-authored-by: Chris B <beanz@abolishcrlf.org>
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