commit eaf23b2480a1c892d86abb7c911d86687a7cfe72
author Allen <zhongyunde@huawei.com> Tue Sep 12 21:15:01 2023 +0800
committer GitHub <noreply@github.com> Tue Sep 12 21:15:01 2023 +0800
tree 810d81caff9adfc6811411704a58433927648b71
parent 70248920fcd804a5825ecf69f24b96a7e340afe6

[GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT (#65830)

Widen the vector elements to 64 bits to make sure it legal instead by
clamping the number of elements. Depend on D153394.

Fixes https://github.com/llvm/llvm-project/issues/63826

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index cfb9595..a5e8024 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2496,6 +2496,17 @@
     return Legalized;
   }
   case TargetOpcode::G_INSERT_VECTOR_ELT: {
+    if (TypeIdx == 0) {
+      Observer.changingInstr(MI);
+      const LLT WideEltTy = WideTy.getElementType();
+
+      widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
+      widenScalarSrc(MI, WideEltTy, 2, TargetOpcode::G_ANYEXT);
+      widenScalarDst(MI, WideTy, 0);
+      Observer.changedInstr(MI);
+      return Legalized;
+    }
+
     if (TypeIdx == 1) {
       Observer.changingInstr(MI);