)]}'
{
  "commit": "eaa7516e15ce50d0e49eecfc4bceb9e6cd91ff8f",
  "tree": "04d8376069e146eb478c0534df711b6487cd58f6",
  "parents": [
    "fb0881f62891e4042725731ec2e4cbc7e8f37e7c"
  ],
  "author": {
    "name": "calm",
    "email": "148254234+calm329@users.noreply.github.com",
    "time": "Wed Jan 14 15:43:11 2026 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Jan 14 15:43:11 2026 -0800"
  },
  "message": "[X86] Lower scalar llvm.clmul intrinsics to PCLMULQDQ (#175189) (#175216)\n\nAdd support for lowering scalar llvm.clmul intrinsics (i8/i16/i32/i64)\nto the PCLMULQDQ hardware instruction on X86 targets with the PCLMUL\nfeature, instead of using the default software expansion.\n\nThe lowering:\n\n- Extends smaller types to the target\u0027s native width (i64 on x86-64, i32\non i686)\n- Uses SCALAR_TO_VECTOR to create vectors (v2i64 on x86-64, v4i32 with\nbitcast to v2i64 on i686)\n- Performs X86ISD::PCLMULQDQ with immediate 0x00\n- Extracts the result and truncates back to the original type\n\ni8/i16/i32 CLMUL is enabled on both 32-bit and 64-bit targets. i64\nCLMUL/CLMULH is only enabled on 64-bit targets.\n\nAlso adds ISD::CLMULH i64 support by extracting the upper element from\nthe v2i64 result.\n\nFixes #175189",
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