)]}'
{
  "commit": "e8a2ce1e9c9db26f2adf4ea6c65eea0299d3a211",
  "tree": "1aeb58d62f86e12cbaed2a3fa23ae6dd0de40ccf",
  "parents": [
    "35a9631279268b6d3d0f0826da0c09e78db6529a"
  ],
  "author": {
    "name": "Jonathan Thackray",
    "email": "jonathan.thackray@arm.com",
    "time": "Mon May 19 17:15:03 2025 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon May 19 17:15:03 2025 +0100"
  },
  "message": "[AArch64] When printing SYS aliases, use explicit `NeedsReg` flag from tablegen (NFC) (#140484)\n\nCurrently, when printing SYS aliases, the first instruction operand is\ncompared with the string constant \"all\" to decide if a register needs to\nbe parsed as the next operand.\n\nFor example, `TLBI VMALLE1IS` contains \"all\" so no register is expected,\nbut `TLBI IPAS2E1IS` doesn\u0027t match, so a register is expected.\n\nFuture AArch64 SYS aliases won\u0027t always match this pattern, so use the\n(already provided) explicit `NeedsReg` bit flag provided in tablegen to\ncheck if a register is required to be parsed. This is already used by\nthe code in `AArch64InstPrinter.cpp`, so now we are consistent in this\nsource file too.\n\nNo test files have been changed, since this is a non-functional change,\nand all AArch64 test cases continue to pass after this change.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "00e8140807735fc5e4da574cc159ec02de09935f",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp",
      "new_id": "e0bd2e55cd959f77a31e77f72458803e155babbb",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp"
    }
  ]
}