commit | e860c166556105c6f9275e130a0c27ae117a5f12 | [log] [tgz] |
---|---|---|
author | Luke Lau <luke@igalia.com> | Wed Jul 03 11:58:53 2024 +0800 |
committer | GitHub <noreply@github.com> | Wed Jul 03 11:58:53 2024 +0800 |
tree | bc62559894b0a83bc5962801a6fab87c80b74180 | |
parent | 0f9fbbb63cfcd2069441aa2ebef622c9716f8dbb [diff] |
[Docs][RISCV] Document RISC-V vector codegen (#96740) This is a revival of https://reviews.llvm.org/D142348, and attempts to document how RVV semantics can be expressed in LLVM IR as well as how codegen works in the backend. Parts of this are taken from the original RFC https://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html, but I've largely rewritten this from the original differential revision to exclude explaining the specification itself and instead just focus on the LLVM specific bits. (I figured that there's better material available elsewhere for learning about RVV itself) I've also updated it to include as much as I know about fixed vector codegen as well as the recent changes to vsetvli insertion.
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