)]}'
{
  "commit": "e7dcf1b7e5574d03d1ce6e7520d5683cfea37706",
  "tree": "b335a4fd520ba824921c5916b5747e805d6a702b",
  "parents": [
    "28156539a9df3fa0d9db47c405c0006fcee9f77f"
  ],
  "author": {
    "name": "Charitha Saumya",
    "email": "136391709+charithaintc@users.noreply.github.com",
    "time": "Thu May 08 13:17:38 2025 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu May 08 13:17:38 2025 -0700"
  },
  "message": "[mlir][xegpu] Add SIMT distribution patterns for UpdateNdOffset and PrefetchNd ops.  (#138033)\n\nThis PR adds support for SIMT distribution of UpdateNdOffset and\nPrefetchNd ops.\n\nFor both these ops distribution will remove the layout attribute from\nthe tensor descriptor type. Everything else remains unchanged.\n\nExample 1:\n\n ```\n   #lo0 \u003d #xegpu.layout\u003cwi_layout \u003d [1, 8], wi_data \u003d [1, 1]\u003e\n   gpu.warp_execute_on_lane_0(%laneid) -\u003e () {\n     ...\n     xegpu.prefetch_nd %arg0 : !xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e\n   }\n ```\n To\n ```\n   %r:2 \u003d gpu.warp_execute_on_lane_0(%laneid) -\u003e (\n   !xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e) {\n     gpu.yield %arg0: !xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e\n   }\n   %1 \u003d unrealized_conversion_cast %r#0: !xegpu.tensor_desc\u003c4x8xf32,\n     #lo0\u003e -\u003e !xegpu.tensor_desc\u003c4x8xf32\u003e\n   xegpu.prefetch_nd %0 : !xegpu.tensor_desc\u003c4x8xf32\u003e\n\n ```\nExample 2:\n ```\n   #lo0 \u003d #xegpu.layout\u003cwi_layout \u003d [1, 8], wi_data \u003d [1, 1]\u003e\n   %r \u003d gpu.warp_execute_on_lane_0(%laneid) -\u003e\n                   (!xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e) {\n     ...\n     %update \u003d xegpu.update_nd_offset %arg0, [%c32, %c16]:\n       !xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e\n     gpu.yield %update\n   }\n   ...\n ```\n To\n ```\n   %r:2 \u003d gpu.warp_execute_on_lane_0(%laneid) -\u003e (vector\u003c4x1xf32\u003e,\n   !xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e) {\n     ...\n     %dead \u003d xegpu.update_nd_offset %arg0, [%c32, %c16]:\n       !xegpu.tensor_desc\u003c4x8xf32, #lo0\u003e gpu.yield %dead, %arg0\n     gup.yield %dead, %arg0, %c32, %c16\n   }\n%0 \u003d xegpu.unrealized_conversion_cast %r#1: !xegpu.tensor_desc\u003c4x8xf32,\n        #lo0\u003e -\u003e !xegpu.tensor_desc\u003c4x8xf32\u003e\n   %1 \u003d xegpu.update_nd_offset %0, [%c32, %c16]:\n     !xegpu.tensor_desc\u003c4x8xf32\u003e\n   ...\n ```",
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