| commit | e697c99b63224069daa3814f536a69fecab8cd4e | [log] [tgz] |
|---|---|---|
| author | Krzysztof Drewniak <Krzysztof.Drewniak@amd.com> | Tue Mar 04 17:19:06 2025 -0600 |
| committer | GitHub <noreply@github.com> | Tue Mar 04 17:19:06 2025 -0600 |
| tree | 0c6e8dab3e73d0a9f14154eb4f44984fd2c64b35 | |
| parent | fa072bd29a109be424e6f4521823529750a55efe [diff] |
[AMDGPU] Add custom MachineValueType entries for buffer fat poiners (#127692) The old hack of returning v5/v6i32 for the fat and strided buffer pointers was causing issuse during vectorization queries that expected to be able to construct a VectorType from the return value of `MVT getPointerType()`. On example is in the test attached to this PR, which used to crash. Now, we define the custom MVT entries, the 160-bit amdgpuBufferFatPointer and 192-bit amdgpuBufferStridedPointer, which are used to represent ptr addrspace(7) and ptr addrspace(9) respectively. Neither of these types will be present at the time of lowering to a SelectionDAG or other MIR - MVT::amdgpuBufferFatPointer is eliminated by the LowerBufferFatPointers pass and amdgpu::bufferStridedPointer is not currently used outside of the SPIR-V translator (which does its own lowering). An alternative solution would be to add MVT::i160 and MVT::i192. We elect not to do this now as it would require changes to unrelated code and runs the risk of breaking any SelectionDAG code that assumes that the MVT series are all powers of two (and so can be split apart and merged back together) in ways that wouldn't be obvious if someone tried to use MVT::i160 in codegen. If i160 is added at some future point, these custom types can be retired.
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