[AMDGPU] Hazard handling for gfx1250 wmma instructions (#149865) If both instructions are xdl WMMA, hazard exists when the first WMMA writes a register (D0) and the second WMMA reads it (A1/B1/Index1). If the first instruction is a xdl WMMA, and the second one is a VALU, three kinds of hazards exist: WMMA writes (D0), VALU reads (Use1); WMMA writes (D0), VALU writes (D1); WMMA reads (A0/B0.Index0), VALU writes (D1). The actual number of hazard slots depends on the categories of the first xdl WMMA as well as whether the second instruction is a xdl WMMA or VALU. If there is not enough unrelated VALUs in between the two instructions, appropriate number (to cover the missing) of V_NOPs will be inserted to satisfy the hazard handling requirements.
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