)]}'
{
  "commit": "e47d3a30881794c99a6de3aa9adc806bf3dc79f6",
  "tree": "601cdf9e21fc497302073b4506ad5c2cf5068a9c",
  "parents": [
    "6c3adaafe3f2139fba5ef3865cbcbba93dbab645"
  ],
  "author": {
    "name": "Peter Smith",
    "email": "peter.smith@arm.com",
    "time": "Tue Apr 01 09:49:27 2025 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Apr 01 09:49:27 2025 +0100"
  },
  "message": "[LLD][AArch64] Increase alignment of AArch64AbsLongThunk to 8 (#133738)\n\nThis permits an AArch64AbsLongThunk to be used in an environment where\nunaligned accesses are disabled.\n\nThe AArch64AbsLongThunk does a load of an 8-byte address. When unaligned\naccesses are disabled this address must be 8-byte aligned.\n\nThe vast majority of AArch64 systems will have unaligned accesses\nenabled in userspace. However, after a reset, before the MMU has been\nenabled, all memory accesses are to \"device\" memory, which requires\naligned accesses. In systems with multi-stage boot loaders a thunk may\nbe required to a later stage before the MMU has been enabled.\n\nAs we only want to increase the alignment when the ldr is used we delay\nthe increase in thunk alignment until we know we are going to write an\nldr. We also need to account for the ThunkSection alignment increase\nwhen this happens.\n\nIn some of the test updates, particularly those with shared CHECK lines\nwith position independent thunks it was easier to ensure that the thunks\nstarted at an 8-byte aligned address in all cases.",
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