)]}'
{
  "commit": "e44646b79594006c9dc7deda6a9ae447243bd9e3",
  "tree": "e8475101e09d82a55a32eb3eb05b0588e42fc19c",
  "parents": [
    "dcab4cb49bfb0aa17df3d3fabe582696100e0d35"
  ],
  "author": {
    "name": "Sam Parker",
    "email": "sam.parker@arm.com",
    "time": "Thu Nov 20 08:57:08 2025 +0000"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Nov 20 08:57:08 2025 +0000"
  },
  "message": "[WebAssembly] Lower ANY_EXTEND_VECTOR_INREG (#167529)\n\nTreat it in the same manner of zero_extend_vector_inreg and generate an\nextend_low_u if possible. This is to try an prevent expensive shuffles\nfrom being generated instead. computeKnownBitsForTargetNode has also\nbeen updated to specify known zeros on extend_low_u. ",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "abd8b2e095ae1f21a99ab30f44ec39aa2cf58c7a",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp",
      "new_id": "98cb7aba562c4d90b4ff6004ec96510b2f4a2d7c",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "d698fad745dfb7481e5a6ccd8e615d461f721cfe",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/WebAssembly/simd-arith.ll",
      "new_id": "60b4a837f7c3103b423bb49799f83e17dc9132b2",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/WebAssembly/simd-arith.ll"
    },
    {
      "type": "modify",
      "old_id": "f7143711394fa15f5fb2131feb4936a5c0c7c1ad",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll",
      "new_id": "70c6baf2be00508e65fe3edc5e174c0e1baae676",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll"
    }
  ]
}