diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll b/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
index 3d52a2c..32f5798 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
@@ -1,6 +1,22 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm | FileCheck %s
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI:       warning: Instruction selection used fallback path for test_sqrdmlah_extracted_lane_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlahq_extracted_lane_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlsh_extracted_lane_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlshq_extracted_lane_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlah_i32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlsh_i32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlah_extract_i32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrdmlsh_extract_i32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_vqrdmlahs_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_vqrdmlahs_lane_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_vqrdmlahs_laneq_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_vqrdmlshs_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_vqrdmlshs_lane_s32
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_vqrdmlshs_laneq_s32
 
 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
@@ -404,15 +420,25 @@
 }
 
 define i32 @test_sqrdmlah_v1i32(i32 %acc, i32 %x, i32 %y) {
-; CHECK-LABEL: test_sqrdmlah_v1i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov s0, w1
-; CHECK-NEXT:    fmov s1, w2
-; CHECK-NEXT:    sqrdmulh v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    fmov s1, w0
-; CHECK-NEXT:    sqadd v0.4s, v1.4s, v0.4s
-; CHECK-NEXT:    fmov w0, s0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_sqrdmlah_v1i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    fmov s0, w1
+; CHECK-SD-NEXT:    fmov s1, w2
+; CHECK-SD-NEXT:    sqrdmulh v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    fmov s1, w0
+; CHECK-SD-NEXT:    sqadd v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT:    fmov w0, s0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_sqrdmlah_v1i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov v0.s[0], w1
+; CHECK-GI-NEXT:    mov v1.s[0], w2
+; CHECK-GI-NEXT:    sqrdmulh v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    mov v1.s[0], w0
+; CHECK-GI-NEXT:    sqadd v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT:    fmov w0, s0
+; CHECK-GI-NEXT:    ret
   %x_vec = insertelement <4 x i32> undef, i32 %x, i64 0
   %y_vec = insertelement <4 x i32> undef, i32 %y, i64 0
   %prod_vec = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x_vec,  <4 x i32> %y_vec)
@@ -443,15 +469,25 @@
 }
 
 define i32 @test_sqrdmlsh_v1i32(i32 %acc, i32 %x, i32 %y) {
-; CHECK-LABEL: test_sqrdmlsh_v1i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov s0, w1
-; CHECK-NEXT:    fmov s1, w2
-; CHECK-NEXT:    sqrdmulh v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    fmov s1, w0
-; CHECK-NEXT:    sqsub v0.4s, v1.4s, v0.4s
-; CHECK-NEXT:    fmov w0, s0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_sqrdmlsh_v1i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    fmov s0, w1
+; CHECK-SD-NEXT:    fmov s1, w2
+; CHECK-SD-NEXT:    sqrdmulh v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    fmov s1, w0
+; CHECK-SD-NEXT:    sqsub v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT:    fmov w0, s0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_sqrdmlsh_v1i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov v0.s[0], w1
+; CHECK-GI-NEXT:    mov v1.s[0], w2
+; CHECK-GI-NEXT:    sqrdmulh v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    mov v1.s[0], w0
+; CHECK-GI-NEXT:    sqsub v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT:    fmov w0, s0
+; CHECK-GI-NEXT:    ret
   %x_vec = insertelement <4 x i32> undef, i32 %x, i64 0
   %y_vec = insertelement <4 x i32> undef, i32 %y, i64 0
   %prod_vec = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x_vec,  <4 x i32> %y_vec)
@@ -568,10 +604,16 @@
 ; Using sqrdmlah intrinsics
 
 define <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) {
-; CHECK-LABEL: test_vqrdmlah_laneq_s16:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sqrdmlah v0.4h, v1.4h, v2.h[7]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlah_laneq_s16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    sqrdmlah v0.4h, v1.4h, v2.h[7]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlah_laneq_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    dup v2.8h, v2.h[7]
+; CHECK-GI-NEXT:    sqrdmlah v0.4h, v1.4h, v2.4h
+; CHECK-GI-NEXT:    ret
 entry:
   %lane = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
   %vqrdmlah_v3.i = tail call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %lane) #4
@@ -579,10 +621,16 @@
 }
 
 define <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) {
-; CHECK-LABEL: test_vqrdmlah_laneq_s32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sqrdmlah v0.2s, v1.2s, v2.s[3]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlah_laneq_s32:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    sqrdmlah v0.2s, v1.2s, v2.s[3]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlah_laneq_s32:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    dup v2.4s, v2.s[3]
+; CHECK-GI-NEXT:    sqrdmlah v0.2s, v1.2s, v2.2s
+; CHECK-GI-NEXT:    ret
 entry:
   %lane = shufflevector <4 x i32> %v, <4 x i32> poison, <2 x i32> <i32 3, i32 3>
   %vqrdmlah_v3.i = tail call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %lane) #4
@@ -644,14 +692,23 @@
 }
 
 define i16 @test_vqrdmlahh_lane_s16(i16 %a, i16 %b, <4 x i16> %c) {
-; CHECK-LABEL: test_vqrdmlahh_lane_s16:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fmov s1, w0
-; CHECK-NEXT:    fmov s2, w1
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    sqrdmlah v1.4h, v2.4h, v0.h[3]
-; CHECK-NEXT:    umov w0, v1.h[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlahh_lane_s16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    fmov s1, w0
+; CHECK-SD-NEXT:    fmov s2, w1
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    sqrdmlah v1.4h, v2.4h, v0.h[3]
+; CHECK-SD-NEXT:    umov w0, v1.h[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlahh_lane_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    rev64 v0.4h, v0.4h
+; CHECK-GI-NEXT:    fmov s1, w0
+; CHECK-GI-NEXT:    fmov s2, w1
+; CHECK-GI-NEXT:    sqrdmlah v1.4h, v2.4h, v0.4h
+; CHECK-GI-NEXT:    umov w0, v1.h[0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = insertelement <4 x i16> undef, i16 %a, i64 0
   %1 = insertelement <4 x i16> undef, i16 %b, i64 0
@@ -677,13 +734,22 @@
 }
 
 define i16 @test_vqrdmlahh_laneq_s16(i16 %a, i16 %b, <8 x i16> %c) {
-; CHECK-LABEL: test_vqrdmlahh_laneq_s16:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fmov s1, w0
-; CHECK-NEXT:    fmov s2, w1
-; CHECK-NEXT:    sqrdmlah v1.4h, v2.4h, v0.h[7]
-; CHECK-NEXT:    umov w0, v1.h[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlahh_laneq_s16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    fmov s1, w0
+; CHECK-SD-NEXT:    fmov s2, w1
+; CHECK-SD-NEXT:    sqrdmlah v1.4h, v2.4h, v0.h[7]
+; CHECK-SD-NEXT:    umov w0, v1.h[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlahh_laneq_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    ext v0.16b, v0.16b, v0.16b, #14
+; CHECK-GI-NEXT:    fmov s1, w0
+; CHECK-GI-NEXT:    fmov s2, w1
+; CHECK-GI-NEXT:    sqrdmlah v1.4h, v2.4h, v0.4h
+; CHECK-GI-NEXT:    umov w0, v1.h[0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = insertelement <4 x i16> undef, i16 %a, i64 0
   %1 = insertelement <4 x i16> undef, i16 %b, i64 0
@@ -708,10 +774,16 @@
 }
 
 define <4 x i16> @test_vqrdmlsh_laneq_s16(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) {
-; CHECK-LABEL: test_vqrdmlsh_laneq_s16:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sqrdmlsh v0.4h, v1.4h, v2.h[7]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlsh_laneq_s16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    sqrdmlsh v0.4h, v1.4h, v2.h[7]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlsh_laneq_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    dup v2.8h, v2.h[7]
+; CHECK-GI-NEXT:    sqrdmlsh v0.4h, v1.4h, v2.4h
+; CHECK-GI-NEXT:    ret
 entry:
   %lane = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
   %vqrdmlsh_v3.i = tail call <4 x i16> @llvm.aarch64.neon.sqrdmlsh.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %lane) #4
@@ -719,10 +791,16 @@
 }
 
 define <2 x i32> @test_vqrdmlsh_laneq_s32(<2 x i32> %a, <2 x i32> %b, <4 x i32> %v) {
-; CHECK-LABEL: test_vqrdmlsh_laneq_s32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sqrdmlsh v0.2s, v1.2s, v2.s[3]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlsh_laneq_s32:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    sqrdmlsh v0.2s, v1.2s, v2.s[3]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlsh_laneq_s32:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    dup v2.4s, v2.s[3]
+; CHECK-GI-NEXT:    sqrdmlsh v0.2s, v1.2s, v2.2s
+; CHECK-GI-NEXT:    ret
 entry:
   %lane = shufflevector <4 x i32> %v, <4 x i32> poison, <2 x i32> <i32 3, i32 3>
   %vqrdmlsh_v3.i = tail call <2 x i32> @llvm.aarch64.neon.sqrdmlsh.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %lane) #4
@@ -784,14 +862,23 @@
 }
 
 define i16 @test_vqrdmlshh_lane_s16(i16 %a, i16 %b, <4 x i16> %c) {
-; CHECK-LABEL: test_vqrdmlshh_lane_s16:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fmov s1, w0
-; CHECK-NEXT:    fmov s2, w1
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    sqrdmlsh v1.4h, v2.4h, v0.h[3]
-; CHECK-NEXT:    umov w0, v1.h[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlshh_lane_s16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    fmov s1, w0
+; CHECK-SD-NEXT:    fmov s2, w1
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    sqrdmlsh v1.4h, v2.4h, v0.h[3]
+; CHECK-SD-NEXT:    umov w0, v1.h[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlshh_lane_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    rev64 v0.4h, v0.4h
+; CHECK-GI-NEXT:    fmov s1, w0
+; CHECK-GI-NEXT:    fmov s2, w1
+; CHECK-GI-NEXT:    sqrdmlsh v1.4h, v2.4h, v0.4h
+; CHECK-GI-NEXT:    umov w0, v1.h[0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = insertelement <4 x i16> undef, i16 %a, i64 0
   %1 = insertelement <4 x i16> undef, i16 %b, i64 0
@@ -817,13 +904,22 @@
 }
 
 define i16 @test_vqrdmlshh_laneq_s16(i16 %a, i16 %b, <8 x i16> %c) {
-; CHECK-LABEL: test_vqrdmlshh_laneq_s16:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fmov s1, w0
-; CHECK-NEXT:    fmov s2, w1
-; CHECK-NEXT:    sqrdmlsh v1.4h, v2.4h, v0.h[7]
-; CHECK-NEXT:    umov w0, v1.h[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_vqrdmlshh_laneq_s16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    fmov s1, w0
+; CHECK-SD-NEXT:    fmov s2, w1
+; CHECK-SD-NEXT:    sqrdmlsh v1.4h, v2.4h, v0.h[7]
+; CHECK-SD-NEXT:    umov w0, v1.h[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vqrdmlshh_laneq_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    ext v0.16b, v0.16b, v0.16b, #14
+; CHECK-GI-NEXT:    fmov s1, w0
+; CHECK-GI-NEXT:    fmov s2, w1
+; CHECK-GI-NEXT:    sqrdmlsh v1.4h, v2.4h, v0.4h
+; CHECK-GI-NEXT:    umov w0, v1.h[0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = insertelement <4 x i16> undef, i16 %a, i64 0
   %1 = insertelement <4 x i16> undef, i16 %b, i64 0