| commit | dda7ce6624e357076fefe55a756ba7181db92ba2 | [log] [tgz] |
|---|---|---|
| author | Sam Elliott <aelliott@qti.qualcomm.com> | Fri Sep 19 01:16:44 2025 +0100 |
| committer | GitHub <noreply@github.com> | Fri Sep 19 00:16:44 2025 +0000 |
| tree | 07746ec18a09c1244d1c9f457a28610e22c7ba38 | |
| parent | 339450fa80bd59ad2d0410a0eb58b8b9981aac10 [diff] |
[RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147) The original patterns for the Xqci select-like instructions used `select`, and marked that ISD node as legal. This is not the usual way that `select` is dealt with in the RISC-V backend. Usually on RISC-V, we expand `select` to `riscv_select_cc` which holds references to the operands of the comparison and the possible values depending on the comparison. In retrospect, this is a much better fit for our instructions, as most of them correspond to specific condition codes, rather than more generic `select` with a truthy/falsey value. This PR moves the Xqci select-like patterns to use `riscv_select_cc` nodes. This applies to the Xqcicm, Xqcics and Xqcicli instruction patterns. In order to match the existing codegen, minor additions had to be made to `translateSetCCForBranch` to ensure that comparisons against specific immediate values are left in a form that can be matched more closely by the instructions. This prevents having to insert additional `li` instructions and use the register forms. There are a few slight regressions: - There are sometimes more `mv` instructions than entirely necessary. I believe these would not be seen with larger examples where the register allocator has more leeway. - In some tests where just one of the three extensions is enabled, codegen falls back to using a branch over a move. With all three extensions enabled (the configuration we most care about), these are not seen. - The generated patterns are very similar to each other - they have similar complexity (7 or 8) and there are still overlaps. Sometimes the choice between two instructions can be affected by the order of the patterns in the tablegen file. One other change is that Xqcicm instructions are prioritised over Xqcics instructions where they have identical patterns. This is done because one of the the Xqcicm instructions is compressible (`qc.mveqi`), while none of the Xqcics instructions are.
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