commit d573aa0156b6aaf0e3cff13958f80d7c227cd656
author Michael Berg <michael_c_berg@apple.com> Thu Apr 18 18:48:57 2019 +0000
committer Michael Berg <michael_c_berg@apple.com> Thu Apr 18 18:48:57 2019 +0000
tree 88ee4dd1f94f87e206d8685db3f2ce8dd6e71802
parent ea3364bf85ef72001b8db3c6fd2dc34f9311b111

[NFC] FMF propagation for GlobalIsel

llvm-svn: 358702

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index f841492..f983b02 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1437,10 +1437,11 @@
     ConstantFP &ZeroForNegation =
         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
-    MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
-        .addDef(Res)
-        .addUse(Zero->getOperand(0).getReg())
-        .addUse(MI.getOperand(1).getReg());
+    unsigned SubByReg = MI.getOperand(1).getReg();
+    unsigned ZeroReg = Zero->getOperand(0).getReg();
+    MachineInstr *SrcMI = MRI.getVRegDef(SubByReg);
+    MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
+                          SrcMI->getFlags());
     MI.eraseFromParent();
     return Legalized;
   }
@@ -1455,10 +1456,7 @@
     unsigned RHS = MI.getOperand(2).getReg();
     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
-    MIRBuilder.buildInstr(TargetOpcode::G_FADD)
-        .addDef(Res)
-        .addUse(LHS)
-        .addUse(Neg);
+    MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
     MI.eraseFromParent();
     return Legalized;
   }