)]}'
{
  "commit": "d28bb1fd786677fca73390a57972d3c722c30dcd",
  "tree": "5509c3952b801fb46796804d534dd9d57ffd2e11",
  "parents": [
    "a7425f900f6467dcbc7847ba0d80382e346a1030"
  ],
  "author": {
    "name": "macurtis-amd",
    "email": "macurtis@amd.com",
    "time": "Fri Aug 01 11:54:25 2025 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 01 11:54:25 2025 -0500"
  },
  "message": "[AMDGPU] Ensure non-reserved CSR spilled regs are live-in (#146427)\n\nFixes:\n```\n*** Bad machine code: Using an undefined physical register ***\n- function:    widget\n- basic block: %bb.0 bb (0x564092cbe140)\n- instruction: $vgpr63 \u003d V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec\n- operand 1:   killed $agpr13\nLLVM ERROR: Found 1 machine code errors.\n```\n\nThe detailed sequence of events that led to this assert:\n\n1. MachineVerifier fails because `$agpr13` is not defined on line 19\nbelow:\n\n   ``` 1: bb.0.bb:\n    2:   successors: %bb.1(0x80000000); %bb.1(100.00%)\n    3:   liveins: $agpr14, $agpr15, $sgpr12, $sgpr13, $sgpr14, \\\n    4:       $sgpr15, $sgpr30, $sgpr31, $sgpr34, $sgpr35, \\\n    5:       $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr48, \\\n    6:       $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, \\\n    7:       $sgpr54, $sgpr55, $sgpr64, $sgpr65, $sgpr66, \\\n    8:       $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, \\\n    9:       $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, \\\n   10:       $sgpr85, $sgpr86, $sgpr87, $sgpr96, $sgpr97, \\\n   11:       $sgpr98, $sgpr99, $vgpr0, $vgpr31, $vgpr40, $vgpr41, \\\n   12:       $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, \\\n   13:       $sgpr10_sgpr11\n   14:   $sgpr16 \u003d COPY $sgpr33\n   15:   $sgpr33 \u003d frame-setup COPY $sgpr32\n   16:   $sgpr18_sgpr19 \u003d S_XOR_SAVEEXEC_B64 -1, \\\n   17:       implicit-def $exec, implicit-def dead $scc, \\\n   18:       implicit $exec\n   19:   $vgpr63 \u003d V_ACCVGPR_READ_B32_e64 killed $agpr13, \\\n   20:       implicit $exec\n   21:   BUFFER_STORE_DWORD_OFFSET killed $vgpr63, \\\n   22:       $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, \\\n   23:       implicit $exec :: (store (s32) into %stack.38, \\\n   24:       addrspace 5)\n   25:   ...\n   26:   $vgpr43 \u003d IMPLICIT_DEF\n   27:   $vgpr43 \u003d SI_SPILL_S32_TO_VGPR $sgpr15, 0, \\\n   28:       killed $vgpr43(tied-def 0)\n   29:   $vgpr43 \u003d SI_SPILL_S32_TO_VGPR $sgpr14, 1, \\\n   30:       killed $vgpr43(tied-def 0)\n   31:   $sgpr100_sgpr101 \u003d S_OR_SAVEEXEC_B64 -1, \\\n   32:       implicit-def $exec, implicit-def dead $scc, \\\n   33:       implicit $exec\n   34:   renamable $agpr13 \u003d COPY killed $vgpr43, implicit $exec\n   ```\n\n2. That instruction is created by\n[`emitCSRSpillStores`](https://github.com/llvm/llvm-project/blob/d599bdeaa49d7a2b1246328630328d23ddda5a47/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp#L977)\n(called by\n[`SIFrameLowering::emitPrologue`](https://github.com/llvm/llvm-project/blob/d599bdeaa49d7a2b1246328630328d23ddda5a47/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp#L1122))\nbecause `$agpr13` is in `WWMSpills`.\n\n   See lines 982, 998, and 993 below.\n\n   ```\n977: // Spill Whole-Wave Mode VGPRs. Save only the inactive lanes of the\nscratch\n978: // registers. However, save all lanes of callee-saved VGPRs. Due to\nthis, we\n   979:   // might end up flipping the EXEC bits twice.\n   980:   Register ScratchExecCopy;\n981: SmallVector\u003cstd::pair\u003cRegister, int\u003e, 2\u003e WWMCalleeSavedRegs,\nWWMScratchRegs;\n982: FuncInfo-\u003esplitWWMSpillRegisters(MF, WWMCalleeSavedRegs,\nWWMScratchRegs);\n   983:   if (!WWMScratchRegs.empty())\n   984:     ScratchExecCopy \u003d\n   985:         buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL,\n986: /*IsProlog*/ true, /*EnableInactiveLanes*/ true);\n   987:\n   988:   auto StoreWWMRegisters \u003d\n   989:       [\u0026](SmallVectorImpl\u003cstd::pair\u003cRegister, int\u003e\u003e \u0026WWMRegs) {\n   990:         for (const auto \u0026Reg : WWMRegs) {\n   991:           Register VGPR \u003d Reg.first;\n   992:           int FI \u003d Reg.second;\n993: buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL,\n   994:                            VGPR, FI, FrameReg);\n   995:         }\n   996:       };\n   997:\n   998:   StoreWWMRegisters(WWMScratchRegs);\n   ```\n\n3. `$agpr13` got added to `WWMSpills` by\n[`SILowerWWMCopies::run`](https://github.com/llvm/llvm-project/blob/59a7185dd9d69cbf737a98f5c2d1cf3d456bee03/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp#L137)\nas it processed the `WWM_COPY` on line 3 below (corresponds to line 34\nabove in point #_1_):\n\n   ```\n1: %45:vgpr_32 \u003d SI_SPILL_S32_TO_VGPR $sgpr15, 0, %45:vgpr_32(tied-def\n0)\n2: %45:vgpr_32 \u003d SI_SPILL_S32_TO_VGPR $sgpr14, 1, %45:vgpr_32(tied-def\n0)\n   3: %44:av_32 \u003d WWM_COPY %45:vgpr_32\n   ```",
  "tree_diff": [
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      "old_path": "llvm/lib/Target/AMDGPU/SIFrameLowering.cpp",
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      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIFrameLowering.cpp"
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      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
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      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir"
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}