commit d0c435c23c6dacb72964f3ce8c8cb814b248e872
author Jim Grosbach <grosbach@apple.com> Fri Sep 16 22:58:42 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Fri Sep 16 22:58:42 2011 +0000
tree 39a0687fe8618c4e1c7a6afb77d9d89018a9b9d0
parent bcfa9a6f89eba176b27e2b36d698ef38426ef987

Thumb2 assembly parsing and encoding for SUB(immediate).

llvm-svn: 139966

llvm/lib/Target/ARM/ARMInstrThumb.td

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index f8198c8..a49f988 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1145,7 +1145,7 @@
 
 // Subtract immediate
 def tSUBi3 :                    // A8.6.210 T1
-  T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
+  T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                    IIC_iALUi,
                    "sub", "\t$Rd, $Rm, $imm3",
                    [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
@@ -1154,8 +1154,8 @@
 }
 
 def tSUBi8 :                    // A8.6.210 T2
-  T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
-                    IIC_iALUi,
+  T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
+                    (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
                     "sub", "\t$Rdn, $imm8",
                     [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;