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llvm / llvm-project / ce2208331d0530db525928a2d427c48f4c5fb8bb / . / llvm / test / Transforms / LoopVectorize / RISCV
tree: a08a9c4e1bfa6443420085ba6a761a769e855376 [path history] [tgz]
  1. defaults.ll
  2. divrem.ll
  3. evl-compatible-loops.ll
  4. force-vect-msg.ll
  5. illegal-type.ll
  6. inloop-reduction.ll
  7. interleaved-accesses-zve32x.ll
  8. interleaved-accesses.ll
  9. interleaved-cost.ll
  10. lit.local.cfg
  11. lmul.ll
  12. low-trip-count.ll
  13. mask-index-type.ll
  14. masked_gather_scatter.ll
  15. ordered-reduction.ll
  16. pr87378-vpinstruction-or-drop-poison-generating-flags.ll
  17. pr88802.ll
  18. reg-usage.ll
  19. riscv-interleaved.ll
  20. riscv-unroll.ll
  21. riscv-vector-reverse.ll
  22. safe-dep-distance.ll
  23. scalable-basics.ll
  24. scalable-reductions.ll
  25. scalable-tailfold.ll
  26. scalable-vf-hint.ll
  27. select-cmp-reduction.ll
  28. short-trip-count.ll
  29. strided-accesses.ll
  30. uniform-load-store.ll
  31. unroll-in-loop-vectorizer.ll
  32. vectorize-force-tail-with-evl-gather-scatter.ll
  33. vectorize-force-tail-with-evl-interleave.ll
  34. vectorize-force-tail-with-evl-iv32.ll
  35. vectorize-force-tail-with-evl-masked-loadstore.ll
  36. vectorize-force-tail-with-evl-no-masking.ll
  37. vectorize-force-tail-with-evl-reverse-load-store.ll
  38. vectorize-vp-intrinsics.ll
  39. vplan-vp-intrinsics.ll
  40. zvl32b.ll