llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.

; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN:   -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s

; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
; RUN:   -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s

; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
; RUN:   -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s

; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
define <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxleqv v5, v5, v5
; CHECK-NEXT:    xxlxor vs0, v3, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    vslw v2, v2, v5
; CHECK-NEXT:    vsraw v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %xor = xor <4 x i32> %B, %C
  %and = and <4 x i32> %B, %C
  %res = select <4 x i1> %A, <4 x i32> %xor, <4 x i32> %and
  ret <4 x i32> %res
}

; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
define <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxlxor v5, v5, v5
; CHECK-NEXT:    xxlxor vs0, v3, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    xxsplti32dx v5, 1, 63
; CHECK-NEXT:    vsld v2, v2, v5
; CHECK-NEXT:    vsrad v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %xor = xor <2 x i64> %B, %C
  %and = and <2 x i64> %B, %C
  %res = select <2 x i1> %A, <2 x i64> %xor, <2 x i64> %and
  ret <2 x i64> %res
}

; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
define <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxleqv v5, v5, v5
; CHECK-NEXT:    xxlnor vs0, v3, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    vslw v2, v2, v5
; CHECK-NEXT:    vsraw v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %or = or <4 x i32> %B, %C
  %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>  ; Vector NOR operation
  %and = and <4 x i32> %B, %C
  %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %and
  ret <4 x i32> %res
}

; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
define <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxlxor v5, v5, v5
; CHECK-NEXT:    xxlnor vs0, v3, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    xxsplti32dx v5, 1, 63
; CHECK-NEXT:    vsld v2, v2, v5
; CHECK-NEXT:    vsrad v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %or = or <2 x i64> %B, %C
  %nor = xor <2 x i64> %or, <i64 -1, i64 -1>  ; Vector NOR operation
  %and = and <2 x i64> %B, %C
  %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %and
  ret <2 x i64> %res
}

; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
define <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxleqv v5, v5, v5
; CHECK-NEXT:    xxleqv vs0, v3, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    vslw v2, v2, v5
; CHECK-NEXT:    vsraw v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %xor = xor <4 x i32> %B, %C
  %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1>  ; Vector eqv operation
  %and = and <4 x i32> %B, %C
  %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %and
  ret <4 x i32> %res
}

; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
define <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxlxor v5, v5, v5
; CHECK-NEXT:    xxleqv vs0, v3, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    xxsplti32dx v5, 1, 63
; CHECK-NEXT:    vsld v2, v2, v5
; CHECK-NEXT:    vsrad v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %xor = xor <2 x i64> %B, %C
  %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1>  ; Vector eqv operation
  %and = and <2 x i64> %B, %C
  %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %and
  ret <2 x i64> %res
}

; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
define <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxleqv v5, v5, v5
; CHECK-NEXT:    xxlnor vs0, v4, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    vslw v2, v2, v5
; CHECK-NEXT:    vsraw v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1>  ; Vector not operation
  %and = and <4 x i32> %B, %C
  %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
  ret <4 x i32> %res
}

; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
define <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxlxor v5, v5, v5
; CHECK-NEXT:    xxlnor vs0, v4, v4
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    xxsplti32dx v5, 1, 63
; CHECK-NEXT:    vsld v2, v2, v5
; CHECK-NEXT:    vsrad v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %not = xor <2 x i64> %C, <i64 -1, i64 -1>  ; Vector not operation
  %and = and <2 x i64> %B, %C
  %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
  ret <2 x i64> %res
}

; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
define <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxleqv v5, v5, v5
; CHECK-NEXT:    xxlnor vs0, v3, v3
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    vslw v2, v2, v5
; CHECK-NEXT:    vsraw v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>  ; Vector not operation
  %and = and <4 x i32> %B, %C
  %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
  ret <4 x i32> %res
}

; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
define <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxlxor v5, v5, v5
; CHECK-NEXT:    xxlnor vs0, v3, v3
; CHECK-NEXT:    xxland vs1, v3, v4
; CHECK-NEXT:    xxsplti32dx v5, 1, 63
; CHECK-NEXT:    vsld v2, v2, v5
; CHECK-NEXT:    vsrad v2, v2, v5
; CHECK-NEXT:    xxsel v2, vs1, vs0, v2
; CHECK-NEXT:    blr
entry:
  %not = xor <2 x i64> %B, <i64 -1, i64 -1>  ; Vector not operation
  %and = and <2 x i64> %B, %C
  %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
  ret <2 x i64> %res
}