)]}'
{
  "commit": "cbb9b0e08ed19b074ff594a1306c3ca3cb8b9913",
  "tree": "e2a7b5164c423a697c298a368d753a2e574fb854",
  "parents": [
    "e974c65774414eceaf789e2464f56e39c9afc210"
  ],
  "author": {
    "name": "Benjamin Maxwell",
    "email": "benjamin.maxwell@arm.com",
    "time": "Thu Nov 06 13:33:55 2025 +0000"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Nov 06 13:33:55 2025 +0000"
  },
  "message": "[AArch64] Lower v1i64 and v2i64 [S|U][MIN|MAX] to SVE when available (#166735)\n\nThe predicate is likely to be hoisted, so in a loop, this would result\nin a single SVE instruction, which should have lower latency.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d08f9b94227a2f57030701ff9984ae47ec9d5111",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AArch64ISelLowering.cpp",
      "new_id": "5defd4872012c445f641aaa7a11d11934dc7ab43",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AArch64ISelLowering.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6696f94d404c5c469f3e46971481591885d2378a",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AArch64/vector-minmax.ll"
    }
  ]
}