; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s

define amdgpu_kernel void @row_filter_C1_D0() #0 {
; GCN-LABEL: row_filter_C1_D0:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_cbranch_scc1 .LBB0_2
; GCN-NEXT:  ; %bb.1: ; %do.body.preheader
; GCN-NEXT:  .LBB0_2: ; %for.inc.1
entry:
  br i1 poison, label %for.inc.1, label %do.body.preheader

do.body.preheader:                                ; preds = %entry
  %tmp = insertelement <4 x i32> zeroinitializer, i32 poison, i32 1
  %undef1 = freeze i1 poison
  br i1 %undef1, label %do.body56.1, label %do.body90

do.body90:                                        ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
  %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ %tmp, %do.body.preheader ]
  %tmp2 = insertelement <4 x i32> %tmp1, i32 poison, i32 2
  %tmp3 = insertelement <4 x i32> %tmp2, i32 poison, i32 3
  %undef3 = freeze i1 poison
  br i1 %undef3, label %do.body124.1, label %do.body.1562.preheader

do.body.1562.preheader:                           ; preds = %do.body124.1, %do.body90
  %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
  %tmp4 = insertelement <4 x i32> poison, i32 poison, i32 1
  br label %for.inc.1

do.body56.1:                                      ; preds = %do.body.preheader
  %tmp5 = insertelement <4 x i32> %tmp, i32 poison, i32 1
  %or.cond472.1 = or i1 poison, poison
  br i1 %or.cond472.1, label %do.body56.2, label %do.body90

do.body56.2:                                      ; preds = %do.body56.1
  %tmp6 = insertelement <4 x i32> %tmp5, i32 poison, i32 1
  br label %do.body90

do.body124.1:                                     ; preds = %do.body90
  %tmp7 = insertelement <4 x i32> %tmp3, i32 poison, i32 3
  br label %do.body.1562.preheader

for.inc.1:                                        ; preds = %do.body.1562.preheader, %entry
  %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ]
  %undef2 = freeze <4 x i32> poison
  %add.i495 = add <4 x i32> %storemerge591, %undef2
  unreachable
}

define amdgpu_ps void @foo() #0 {
; GCN-LABEL: foo:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_mov_b64 s[0:1], -1
; GCN-NEXT:    s_cbranch_scc0 .LBB1_2
; GCN-NEXT:  ; %bb.1: ; %bb24
; GCN-NEXT:    s_mov_b64 s[0:1], 0
; GCN-NEXT:  .LBB1_2: ; %Flow1
; GCN-NEXT:    s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT:    s_cbranch_vccz .LBB1_4
; GCN-NEXT:  ; %bb.3: ; %bb9
; GCN-NEXT:    image_sample v[0:1], v0, s[0:7], s[0:3] dmask:0xa
; GCN-NEXT:    s_branch .LBB1_5
; GCN-NEXT:  .LBB1_4:
; GCN-NEXT:    v_mov_b32_e32 v1, 0
; GCN-NEXT:    v_mov_b32_e32 v0, v1
; GCN-NEXT:  .LBB1_5: ; %bb14
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_mul_f32_e32 v0, 0x41280000, v0
; GCN-NEXT:    v_mul_f32_e32 v1, 0x41380000, v1
; GCN-NEXT:    exp mrt0 v1, v0, v0, v0 done vm
; GCN-NEXT:    s_endpgm
bb:
  %undef0 = freeze i1 poison
  br i1 %undef0, label %bb2, label %bb1

bb1:                                              ; preds = %bb
  %undef1 = freeze i1 poison
  br i1 %undef1, label %bb4, label %bb6

bb2:                                              ; preds = %bb4, %bb
  %tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ]
  br i1 poison, label %bb9, label %bb13

bb4:                                              ; preds = %bb7, %bb6, %bb1
  %tmp5 = phi float [ poison, %bb1 ], [ poison, %bb6 ], [ %tmp8, %bb7 ]
  br label %bb2

bb6:                                              ; preds = %bb1
  %undef2 = freeze i1 poison
  br i1 %undef2, label %bb7, label %bb4

bb7:                                              ; preds = %bb6
  %tmp8 = fmul float poison, poison
  br label %bb4

bb9:                                              ; preds = %bb2
  %tmp10 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
  %tmp11 = extractelement <4 x float> %tmp10, i32 1
  %tmp12 = extractelement <4 x float> %tmp10, i32 3
  br label %bb14

bb13:                                             ; preds = %bb2
  br i1 poison, label %bb23, label %bb24

bb14:                                             ; preds = %bb27, %bb24, %bb9
  %tmp15 = phi float [ %tmp12, %bb9 ], [ poison, %bb27 ], [ 0.000000e+00, %bb24 ]
  %tmp16 = phi float [ %tmp11, %bb9 ], [ poison, %bb27 ], [ %tmp25, %bb24 ]
  %tmp17 = fmul float 1.050000e+01, %tmp16
  %tmp18 = fmul float 1.150000e+01, %tmp15
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp18, float %tmp17, float %tmp17, float %tmp17, i1 true, i1 true) #0
  ret void

bb23:                                             ; preds = %bb13
  br i1 poison, label %bb24, label %bb26

bb24:                                             ; preds = %bb26, %bb23, %bb13
  %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ]
  br i1 poison, label %bb27, label %bb14

bb26:                                             ; preds = %bb23
  br label %bb24

bb27:                                             ; preds = %bb24
  br label %bb14
}


declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1

attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX6: {{.*}}
; GFX8: {{.*}}