; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -relocation-model=pic %s -o - | FileCheck %s

; Tests come from "clang/test/CodeGen/ms-inline-asm-variables.c"
; int gVar;
; void t1() {
;  __asm add eax, dword ptr gVar[rax]
;  __asm add dword ptr [rax+gVar], eax
;  __asm add ebx, dword ptr gVar[271 - 82 + 81 + rbx]
;  __asm add dword ptr [rbx + gVar + 828], ebx
;  gVar = 3;
; }
;
; void t2(void) {
;  int lVar;
;  __asm mov eax, dword ptr lVar[rax]
;  __asm mov dword ptr [rax+lVar], eax
;  __asm mov ebx, dword ptr lVar[271 - 82 + 81 + rbx]
;  __asm mov dword ptr [rbx + lVar + 828], ebx
;  __asm mov 5 + 8 + 13 + 21[lVar + rbx], eax
;  lVar = 2;
; }

@gVar = global i32 0, align 4

; Function Attrs: noinline nounwind optnone uwtable
define void @t1() #0 {
; CHECK-LABEL: t1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rbp
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    .cfi_offset %rbp, -16
; CHECK-NEXT:    movq %rsp, %rbp
; CHECK-NEXT:    .cfi_def_cfa_register %rbp
; CHECK-NEXT:    pushq %rbx
; CHECK-NEXT:    .cfi_offset %rbx, -24
; CHECK-NEXT:    movq gVar@GOTPCREL(%rip), %rcx
; CHECK-NEXT:    #APP
; CHECK-EMPTY:
; CHECK-NEXT:    addl (%rcx,%rax), %eax
; CHECK-NEXT:    addl %eax, (%rcx,%rax)
; CHECK-NEXT:    addl 270(%rcx,%rbx), %ebx
; CHECK-NEXT:    addl %ebx, 828(%rcx,%rbx)
; CHECK-EMPTY:
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    movq gVar@GOTPCREL(%rip), %rax
; CHECK-NEXT:    movl $3, (%rax)
; CHECK-NEXT:    popq %rbx
; CHECK-NEXT:    popq %rbp
; CHECK-NEXT:    .cfi_def_cfa %rsp, 8
; CHECK-NEXT:    retq
entry:
  call void asm sideeffect inteldialect "add eax, dword ptr $2[rax]\0A\09add dword ptr $0[rax], eax\0A\09add ebx, dword ptr $3[rbx + $$270]\0A\09add dword ptr $1[rbx + $$828], ebx", "=*m,=*m,*m,*m,~{eax},~{ebx},~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar) #1
  store i32 3, ptr @gVar, align 4
  ret void
}

; Function Attrs: noinline nounwind optnone uwtable
define void @t2() #0 {
; CHECK-LABEL: t2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rbp
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    .cfi_offset %rbp, -16
; CHECK-NEXT:    movq %rsp, %rbp
; CHECK-NEXT:    .cfi_def_cfa_register %rbp
; CHECK-NEXT:    pushq %rbx
; CHECK-NEXT:    .cfi_offset %rbx, -24
; CHECK-NEXT:    #APP
; CHECK-EMPTY:
; CHECK-NEXT:    movl -12(%rbp,%rax), %eax
; CHECK-NEXT:    movl %eax, -12(%rbp,%rax)
; CHECK-NEXT:    movl 258(%rbp,%rbx), %ebx
; CHECK-NEXT:    movl %ebx, 816(%rbp,%rbx)
; CHECK-NEXT:    movl %eax, 35(%rbp,%rbx)
; CHECK-EMPTY:
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    movl $2, -12(%rbp)
; CHECK-NEXT:    popq %rbx
; CHECK-NEXT:    popq %rbp
; CHECK-NEXT:    .cfi_def_cfa %rsp, 8
; CHECK-NEXT:    retq
entry:
  %lVar = alloca i32, align 4
  call void asm sideeffect inteldialect "mov eax, dword ptr $3[rax]\0A\09mov dword ptr $0[rax], eax\0A\09mov ebx, dword ptr $4[rbx + $$270]\0A\09mov dword ptr $1[rbx + $$828], ebx\0A\09mov $2[rbx + $$47], eax", "=*m,=*m,=*m,*m,*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar, ptr elementtype(i32) %lVar) #1
  store i32 2, ptr %lVar, align 4
  ret void
}

attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0}

!0 = !{i32 1, !"wchar_size", i32 4}