[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion.
llvm-svn: 329339
diff --git a/llvm/test/CodeGen/X86/extractelement-legalization-store-ordering.ll b/llvm/test/CodeGen/X86/extractelement-legalization-store-ordering.ll
index a2aa23b..3752ebd 100644
--- a/llvm/test/CodeGen/X86/extractelement-legalization-store-ordering.ll
+++ b/llvm/test/CodeGen/X86/extractelement-legalization-store-ordering.ll
@@ -15,23 +15,22 @@
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT: paddd (%ecx), %xmm0
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
-; CHECK-NEXT: movdqa %xmm0, (%ecx)
-; CHECK-NEXT: movl (%ecx), %esi
-; CHECK-NEXT: movl 4(%ecx), %edi
-; CHECK-NEXT: shll $4, %edx
-; CHECK-NEXT: movl 8(%ecx), %ebx
-; CHECK-NEXT: movl 12(%ecx), %ecx
-; CHECK-NEXT: movl %esi, 12(%eax,%edx)
-; CHECK-NEXT: movl %edi, (%eax,%edx)
-; CHECK-NEXT: movl %ebx, 8(%eax,%edx)
-; CHECK-NEXT: movl %ecx, 4(%eax,%edx)
+; CHECK-NEXT: paddd (%edx), %xmm0
+; CHECK-NEXT: movdqa %xmm0, (%edx)
+; CHECK-NEXT: movl (%edx), %esi
+; CHECK-NEXT: movl 4(%edx), %edi
+; CHECK-NEXT: shll $4, %ecx
+; CHECK-NEXT: movl 8(%edx), %ebx
+; CHECK-NEXT: movl 12(%edx), %edx
+; CHECK-NEXT: movl %esi, 12(%eax,%ecx)
+; CHECK-NEXT: movl %edi, (%eax,%ecx)
+; CHECK-NEXT: movl %ebx, 8(%eax,%ecx)
+; CHECK-NEXT: movl %edx, 4(%eax,%ecx)
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: retl
-; CHECK-NEXT: ## -- End function
entry:
%0 = bitcast i32* %y to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 16
