commit | c6bb36a3d026a53152ed1635c41dbfad3664ecd5 | [log] [tgz] |
---|---|---|
author | Craig Topper <craig.topper@intel.com> | Thu Apr 05 20:04:06 2018 +0000 |
committer | Craig Topper <craig.topper@intel.com> | Thu Apr 05 20:04:06 2018 +0000 |
tree | f3c49e71e562c26ad669ed8808f964c68d8da95e | |
parent | 650fd6c31c99277e0b9c18a252a325001efa34f7 [diff] |
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge. We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. llvm-svn: 329339