commit c65ac865c394179e4144ecd8796beb96c46d09db
author Aditya Nandakumar <aditya_nandakumar@apple.com> Wed Aug 14 01:23:33 2019 +0000
committer Aditya Nandakumar <aditya_nandakumar@apple.com> Wed Aug 14 01:23:33 2019 +0000
tree d054de651cafbbbf6fcad4067bee9995d1131d44
parent 21872bc9bf374db7f7f340758ac9bf262b892a53

[GlobalISel]: Fix lowering of G_Shuffle_vector where we pick up the wrong source index

https://reviews.llvm.org/D66182

llvm-svn: 368781

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 4d7db27..ad1a41b 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3824,7 +3824,6 @@
   LLT Src0Ty = MRI.getType(Src0Reg);
   LLT DstTy = MRI.getType(DstReg);
   LLT EltTy = DstTy.getElementType();
-  int NumElts = DstTy.getNumElements();
   LLT IdxTy = LLT::scalar(32);
 
   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
@@ -3846,6 +3845,7 @@
     if (Src0Ty.isScalar()) {
       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
     } else {
+      int NumElts = Src0Ty.getNumElements();
       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);