)]}'
{
  "commit": "c50ed05cada308dea282e026cc782a9ea3ab0c29",
  "tree": "b37616b9ffad72145fbae68d2a30cacf0b4a4ee5",
  "parents": [
    "2f237670b1f1ed792a3b1b6a12f8e9af08685983"
  ],
  "author": {
    "name": "Brox Chen",
    "email": "guochen2@amd.com",
    "time": "Wed Aug 20 10:26:49 2025 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Aug 20 10:26:49 2025 -0400"
  },
  "message": "[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)\n\nrecreate this patch from\nhttps://github.com/llvm/llvm-project/pull/153894\n\nIt seems ISel sliently ignore the `i64 \u003d zext i16` with a chained\n`reg_sequence` pattern and thus this is causing a selection failure in\nhip test. Recreate a new patch with an alternative pattern, and added a\nll test global-extload-gfx11plus.ll",
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